System Bus; Kn430 Cpu - DEC 4000 AXP Service Manual

6.1.1 System Bus

The system bus interconnects the CPUs, memory modules, and I/O module. The
I/O module provides access to basic I/O functions (network, storage devices, and
console program). The I/O module also is the adapter to the I/O expansion bus,
Futurebus+.
The system bus is a shared-memory bus designed to support the Alpha AXP
architecture and up to two processors. It supports a ''snooping'' protocol that
allows a CPU's first-level write-through cache and second-level write-back cache
to maintain consistent data with another processor's caches, system memory, and
the I/O port on a transaction-by-transaction basis.
The system bus is a synchronous, multiplexed interconnect that can transfer
a 34-bit address or a 128-bit data with 32-bit parity in a bus transaction. Two
CPU modules and an I/O module arbitrate for the system bus via a prioritized
scheme that allows the I/O module to interleave with the two CPU modules. The
arbitration function and system bus clock generators are located on the CPU 0
module.

6.1.1.1 KN430 CPU

The KN430 CPU module is based upon the DECchip 21064 processor, designed
and manufactured by Digital. The system supports up to two CPU modules in a
symmetric multiprocessing configuration. The first CPU is installed in slot 0. For
symmetric multiprocessing (SMP), a second CPU is installed in slot 1. Figure 6–5
provides a block diagram of the CPU module.
System Configuration and Setup 6–7