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TMS320DM644x
Texas Instruments TMS320DM644x Processor Manuals
Manuals and User Guides for Texas Instruments TMS320DM644x Processor. We have
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Texas Instruments TMS320DM644x Processor manual available for free PDF download: User Manual
Texas Instruments TMS320DM644x User Manual (61 pages)
DMSoC Multimedia Card (MMC)/Secure Digital(SD) Card Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.69 MB
Table of Contents
Table of Contents
3
Preface
7
1 Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
9
Supported Use Case Statement
10
Industry Standard(S) Compliance Statement
10
2 Peripheral Architecture
10
MMC/SD Card Controller Block Diagram
10
MMC/SD Controller Interface Diagram
11
MMC Configuration and SD Configuration Diagram
11
Clock Control
12
MMC/SD Controller Clocking Diagram
12
Signal Descriptions
13
Protocol Descriptions
13
MMC/SD Controller Pins Used in each Mode
13
MMC/SD Mode Write Sequence Timing Diagram
14
MMC/SD Mode Write Sequence
14
Data Flow in the Input/Output FIFO
15
MMC/SD Mode Read Sequence Timing Diagram
15
MMC/SD Mode Read Sequence
15
FIFO Operation Diagram
16
Data Flow in the Data Registers (MMCDRR and MMCDXR)
17
Little-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA
17
Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA
18
FIFO Operation During Card Read Operation
19
FIFO Operation During Card Read Diagram
20
FIFO Operation During Card Write Operation
21
FIFO Operation During Card Write Diagram
22
Reset Considerations
23
Initialization
23
2.10 Interrupt Support
27
Description of MMC/SD Interrupt Requests
27
2.11 DMA Event Support
28
2.12 Power Management
28
2.13 Emulation Considerations
28
3 Procedures for Common Operations
29
Card Identification Operation
29
MMC Card Identification Procedure
30
SD Card Identification Procedure
31
MMC/SD Mode Single-Block Write Operation Using CPU
32
MMC/SD Mode Single-Block Write Operation
33
MMC/SD Mode Single-Block Write Operation Using the EDMA
34
MMC/SD Mode Single-Block Read Operation Using the CPU
34
MMC/SD Mode Single-Block Read Operation Using EDMA
35
MMC/SD Mode Single-Block Read Operation
35
MMC/SD Mode Multiple-Block Write Operation Using CPU
36
MMC/SD Multiple-Block Write Operation
37
MMC/SD Mode Multiple-Block Write Operation Using EDMA
38
MMC/SD Mode Multiple-Block Read Operation Using CPU
38
MMC/SD Mode Multiple-Block Read Operation Using EDMA
39
MMC/SD Mode Multiple-Block Read Operation
39
4 Registers
40
Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
40
MMC Control Register (MMCCTL)
41
MMC Control Register (MMCCTL) Field Descriptions
41
MMC Memory Clock Control Register (MMCCLK)
42
MMC Memory Clock Control Register (MMCCLK) Field Descriptions
42
MMC Status Register 0 (MMCST0)
43
MMC Status Register 0 (MMCST0) Field Descriptions
43
MMC Status Register 1 (MMCST1)
45
MMC Status Register 1 (MMCST1) Field Descriptions
45
MMC Interrupt Mask Register (MMCIM)
46
MMC Interrupt Mask Register (MMCIM) Field Descriptions
46
MMC Response Time-Out Register (MMCTOR)
47
MMC Response Time-Out Register (MMCTOR) Field Descriptions
47
MMC Data Read Time-Out Register (MMCTOD)
48
MMC Data Read Time-Out Register (MMCTOD) Field Descriptions
48
MMC Block Length Register (MMCBLEN)
49
MMC Block Length Register (MMCBLEN) Field Descriptions
49
MMC Number of Blocks Register (MMCNBLK)
50
MMC Number of Blocks Counter Register (MMCNBLC)
50
MMC Number of Blocks Register (MMCNBLK) Field Descriptions
50
MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions
50
MMC Data Receive Register (MMCDRR)
51
MMC Data Transmit Register (MMCDXR)
51
MMC Data Receive Register (MMCDRR) Field Descriptions
51
MMC Data Transmit Register (MMCDXR) Field Descriptions
51
MMC Command Register (MMCCMD)
52
MMC Command Register (MMCCMD) Field Descriptions
52
Command Format
53
MMC Argument Register (MMCARGHL)
54
MMC Argument Register (MMCARGHL) Field Descriptions
54
MMC Response Register 0 and 1 (MMCRSP01)
55
MMC Response Register 2 and 3 (MMCRSP23)
55
MMC Response Register 4 and 5 (MMCRSP45)
55
MMC Response Register 6 and 7 (MMCRSP67)
55
R1, R3, R4, R5, or R6 Response (48 Bits)
56
R2 Response (136 Bits)
56
MMC Data Response Register (MMCDRSP)
57
MMC Command Index Register (MMCCIDX)
57
MMC Data Response Register (MMCDRSP) Field Descriptions
57
MMC Command Index Register (MMCCIDX) Field Descriptions
57
MMC FIFO Control Register (MMCFIFOCTL)
58
MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions
58
Document Revision History
59
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