Burst Priority Register (Bprio); Burst Priority Register (Bprio) Field Descriptions - Texas Instruments DM648 DSP User Manual

DDR2 Memory Controller Registers
4.7

Burst Priority Register (BPRIO)

The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory
controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of
the oldest command in the command FIFO after a set number of transfers have been made. The
PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller
raises the priority of the oldest command. The BPRIO is shown in
See Section 2.7.2
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-8 Reserved
7-0 PRIO_RAISE
44 DSP DDR2 Memory Controller
for more details on command starvation.
Figure 26. Burst Priority Register (BPRIO)
R-0
Table 24. Burst Priority Register (BPRIO) Field Descriptions
Value Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Number of memory transfers after which the DDR2 memory controller will elevate the priority of the
oldest command in the command FIFO. Setting this field to FFh disables this feature, thereby
allowing old commands to stay in the FIFO indefinitely.
0 1 memory transfer
1 2 memory transfers
2 3 memory transfers
3-FEh 4-FFh memory transfers
FFh Feature disabled, commands can stay in command FIFO indefinitely
Figure 26
Reserved
R-0
8 7
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and described in Table
PRIO_RAISE
R/W-0xFF
SPRUEK5A – October 2007
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24.
16
0