Sign In
Upload
Manuals
Brands
Texas Instruments Manuals
Controller
TMS320DM646 Series
Texas Instruments TMS320DM646 Series Manuals
Manuals and User Guides for Texas Instruments TMS320DM646 Series. We have
2
Texas Instruments TMS320DM646 Series manuals available for free PDF download: User Manual
Texas Instruments TMS320DM646 Series User Manual (47 pages)
DMSoC VLYNQ Port
Brand:
Texas Instruments
| Category:
Network Card
| Size: 0.38 MB
Table of Contents
Table of Contents
3
List of Figures
5
Preface
7
Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
10
Industry Standard(S) Compliance Statement
10
Architecture
11
Clock Control
11
External Clock Block Diagram
11
Internal Clock Block Diagram
11
Signal Descriptions
12
Protocol Description
12
VLYNQ Port Pins
12
VLYNQ Functional Description
13
VLYNQ Module Structure
13
Write Operations
14
Read Operations
15
Initialization
16
Auto Negotiation
16
Address Translation
16
Example Address Memory Map
17
Address Translation Example (Single Mapped Region)
17
Address Translation Example (Single Mapped Region)
18
Flow Control
19
Reset Considerations
20
2.10 Interrupt Support
20
VLYNQ Interrupt
20
Interrupt Generation Mechanism Block Diagram
21
2.11 DMA Event Support
23
2.12 Power Management
23
2.13 Emulation Considerations
24
2.14 Programming Guide
24
Registers
24
VLYNQ Register Address Space
24
Revision Register (REVID)
25
VLYNQ Port Controller Registers
25
Revision Register (REVID) Field Descriptions
25
Control Register (CTRL)
26
Control Register (CTRL) Field Descriptions
26
Status Register (STAT)
28
Status Register (STAT) Field Descriptions
28
Interrupt Priority Vector Status/Clear Register (INTPRI)
30
Interrupt Status/Clear Register (INTSTATCLR)
30
Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions
30
Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions
30
Interrupt Pending/Set Register (INTPENDSET)
31
Interrupt Pointer Register (INTPTR)
31
Interrupt Pending/Set Register (INTPENDSET) Field Descriptions
31
Interrupt Pointer Register (INTPTR) Field Descriptions
31
Transmit Address Map Register (XAM)
32
Address Map Register (XAM) Field Descriptions
32
Receive Address Map Size 1 Register (RAMS1)
33
Receive Address Map Offset 1 Register (RAMO1)
33
Receive Address Map Size 1 Register (RAMS1) Field Descriptions
33
Receive Address Map Offset 1 Register (RAMO1) Field Descriptions
33
Receive Address Map Size 2 Register (RAMS2)
34
Receive Address Map Offset 2 Register (RAMO2)
34
Receive Address Map Size 2 Register (RAMS2) Field Descriptions
34
Receive Address Map Offset 2 Register (RAMO2) Field Descriptions
34
Receive Address Map Size 3 Register (RAMS3)
35
Receive Address Map Offset 3 Register (RAMO3)
35
Receive Address Map Size 3 Register (RAMS3) Field Descriptions
35
Receive Address Map Offset 3 Register (RAMO3) Field Descriptions
35
Receive Address Map Size 4 Register (RAMS4)
36
Receive Address Map Offset 4 Register (RAMO4)
36
Receive Address Map Size 4 Register (RAMS4) Field Descriptions
36
Receive Address Map Offset 4 Register (RAMO4) Field Descriptions
36
Chip Version Register (CHIPVER)
37
Auto Negotiation Register (AUTNGO)
37
Chip Version Register (CHIPVER) Field Descriptions
37
Auto Negotiation Register (AUTNGO) Field Descriptions
37
Remote Configuration Registers
38
VLYNQ Port Remote Controller Registers
38
Appendix A VLYNQ Protocol Specifications
39
Special 8B/10B Code Groups
39
Supported Ordered Sets
39
VLYNQ 2.0 Packet Format
40
Packet Format (10-Bit Symbol Representation)
40
Packet Format (10-Bit Symbol Representation) Description
41
VLYNQ 2.X Packets
42
Appendix B Write/Read Performance
44
Write Performance
44
Scaling Factors
45
Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)
45
Read Performance
46
Relative Performance with Various Latencies
46
Advertisement
Texas Instruments TMS320DM646 Series User Manual (52 pages)
DMSoC ATA Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.39 MB
Table of Contents
Table of Contents
3
Preface
5
Introduction
7
Purpose of the Peripheral
7
Features
7
Functional Block Diagram
8
Supported Use Cases
8
ATA Controller Block Diagram
8
Industry Standard(S) Compliance
9
Terminology Used in this Document
9
Architecture
9
Clock Control
9
Signal Descriptions
10
Supported ATA Controller Signals
10
Pin Multiplexing
12
Protocol Description(S)
12
Unsupported ATA Controller Signals
12
General Architecture
13
DMA and PIO Data Transaction Overview
18
Physical Region Descriptor (PRD) Table Entry
19
Description of Single Physical Region Descriptor (PRD) Table Entry
19
Attached Device Reset Considerations
22
Initialization
23
Interrupt Support
26
ATA Controller Interrupt
26
Identifying the ATA Controller Interrupt Sources
27
2.10 EDMA Event Support
29
DMA Driven Interrupt Conditions
29
2.11 Power Management
30
2.12 Emulation Considerations
30
Use Cases
30
Interfacing to a Standard ATA/ATAPI Device
30
ATA/ATAPI Device Interface Connections for a Standard ATA/ATAPI Device
30
Interfacing to a Standard ATA/ATAPI Device through a Level-Shifter
31
Interfacing to Compact Flash
32
ATA/ATAPI Device Interface Connections for a Standard ATA/ATAPI Device through a Level-Shifter
32
ATA/ATAPI Device Interface Connections for a Compact Flash Device
33
Registers
34
ATA Controller Registers in the Attached Device
34
Primary IDE Channel DMA Control Register (BMICP)
35
ATA Host Controller Registers
34
Primary IDE Channel DMA Control Register (BMICP) Field Descriptions
35
Primary IDE Channel DMA Status Register (BMISP)
36
Primary IDE Channel DMA Status Register (BMISP) Field Descriptions
36
Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP)
37
Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) Field Descriptions
37
Primary IDE Channel Timing Register (IDETIMP)
38
Primary IDE Channel Timing Register (IDETIMP) Field Descriptions
38
IDE Controller Status Register (IDESTAT)
39
IDE Controller Status Register (IDESTAT) Field Descriptions
39
Ultra-DMA Control Register (UDMACTL)
40
Ultra-DMA Control Register (UDMACTL) Field Descriptions
40
Miscellaneous Control Register (MISCCTL)
41
Miscellaneous Control Register (MISCCTL) Field Descriptions
41
Task File Register Strobe Timing Register (REGSTB)
42
Task File Register Strobe Timing Register (REGSTB) Field Descriptions
42
Task File Register Recovery Timing Register (REGRCVR)
43
Task File Register Recovery Timing Register (REGRCVR) Field Descriptions
43
Data Register Access PIO Strobe Timing Register (DATSTB)
44
Data Register Access PIO Strobe Timing Register (DATSTB) Field Descriptions
44
Data Register Access PIO Recovery Timing Register (DATRCVR)
45
Data Register Access PIO Recovery Timing Register (DATRCVR) Field Descriptions
45
Multiword DMA Strobe Timing Register (DMASTB)
46
Multiword DMA Strobe Timing Register (DMASTB) Field Descriptions
46
Multiword DMA Recovery Timing Register (DMARCVR)
47
Multiword DMA Recovery Timing Register (DMARCVR) Field Descriptions
47
Ultra-DMA Strobe Timing Register (UDMASTB)
48
Ultra-DMA Strobe Timing Register (UDMASTB) Field Descriptions
48
Ultra-DMA Ready-To-Pause Timing Register (UDMATRP)
49
Ultra-DMA Ready-To-Pause Timing Register (UDMATRP) Field Descriptions
49
Ultra-DMA Timing Envelope Register (UDMATENV)
50
Ultra-DMA Timing Envelope Register (UDMATENV) Field Descriptions
50
Primary IO Ready Timer Configuration Register (IORDYTMP)
51
Primary IO Ready Timer Configuration Register (IORDYTMP) Field Descriptions
51
Advertisement
Related Products
Texas Instruments TMS320DM644x
Texas Instruments TMS320DM647
Texas Instruments TMS320DM357
Texas Instruments TMS320C6455
Texas Instruments TMS320C6454
Texas Instruments TMS320C674X
Texas Instruments TMS320C6452 DSP
Texas Instruments TMS320C6742
Texas Instruments TMS320C6748
texas instruments TMS320x281 series
Texas Instruments Categories
Motherboard
Control Unit
Microcontrollers
Computer Hardware
Calculator
More Texas Instruments Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL