Advanced Chipset Features; Dram Timing Selectable; Cas Latency Time; Active To Precharge Delay - Intel MAT-880 User Manual

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.

DRAM Timing Selectable

CAS Latency Time

Active to Precharge Delay

DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
DRAM Data Integrity Mode
MGM Core Frequency
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole at 15M-16M
Delayed Transaction
Delay Prior to Thermal
AGP Aperture Size (MB)
** On-Chip VGA Setting **
On-Chip VGA
On-Chip Frame Buffer Size
Boot Display
Panel Scaling
Panel Number
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is By SPD.
CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The
system board designer should set the values in this field, depending on
the DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU.
Active to Precharge Delay
The default setting for the Active to Precharge Delay is 7.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
By SPD
2
6
3
3
ECC
Auto Max 266MHz
Enabled
Enabled
Disabled
Enabled
16 Min
64
Enabled
32MB
CRT+LVDS
Auto
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MAT-880 User' s Manual
BIOS SETUP
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