Operand Alignment; Transfer Bus Cycles For Bytes, Words And Dwords - Intel Quark SoC X1000 Core Developer's Manual

Table 65. Generating A0, A1 and BHE# from the Intel
Enables (Sheet 2 of 2)
BE3#
†0
†0
KEY:
† =a non-occurring pattern of Byte Enables; either none are asserted or the pattern has byte
enables asserted for non-contiguous bytes
10.1.5

Operand Alignment

Physical 4-byte words begin at addresses that are multiples of four. It is possible to
transfer a logical operand that spans more than one physical 4-byte word of memory or
I/O at the expense of extra cycles. Examples are 4-byte operands beginning at
addresses that are not evenly divisible by 4, or 2-byte words split between two physical
4-byte words. These are referred to as unaligned transfers.
Operand alignment and data bus size dictate when multiple bus cycles are required.
Table 66
lengths, alignment, and data bus sizing. When multiple cycles are required to transfer a
multibyte logical operand, the highest-order bytes are transferred first. For example,
when the processor executes a 4-byte unaligned read beginning at byte location 11 in
the 4-byte aligned space, the three high-order bytes are read in the first bus cycle. The
low byte is read in a subsequent bus cycle.
Table 66.

Transfer Bus Cycles for Bytes, Words and Dwords

Physical Byte Address in
Memory (Low Order Bits)
Transfer Cycles over 32-Bit
Bus
Transfer Cycles over 16-Bit
Bus
(† = BS#16 asserted)
Transfer Cycles over 8-Bit
Bus
(‡ = BS8# Asserted)
KEY:
b = byte transferh = high-order portion4-Byte Operand
w = 2-byte transferl = low-order portion
3 = 3-byte transferm = mid-order portion
d = 4-byte transfer
The function of unaligned transfers with dynamic bus sizing is not obvious. When the
external systems asserts BS16# or BS8#, forcing extra cycles, low-order bytes or
words are transferred first (opposite to the example above). When the Intel
SoC X1000 Core requests a 4-byte read and the external system asserts BS16#, the
lower two bytes are read first followed by the upper two bytes.
®
Intel Quark SoC X1000 Core
Developer's Manual
192
BE2# BE1# BE0#
0 1 1
1 1 1
describes the transfer cycles generated for all combinations of logical operand
1
xx
b
b
b
®
Quark SoC X1000 Core Byte
First Cache Fill Cycle
A0 A1 BHE#
0 0
0 0
Byte-Length of Logical Operand
2
00 01 10 11
hb
w w w
lb
lb † hb
w w
hb † lb
lb ‡ lb ‡ lb ‡ hb
hb ‡ hb‡ hb ‡ lb
®
Intel Quark Core—Bus Operation
Any Other Cycle
A0 A1
0 0 1
0 1 1
4
00 01 10
hb hw
d
l3 lw
hb
lw † hw
lb †
hw † lw
mw †
lb ‡ hb mhb ‡
mlb ‡ lb ‡ hb ‡
mhb ‡ mlb ‡ lb ‡
hb ‡ mhb ‡ mlb ‡
lb mlb mhb
↑byte with
↑ byte with
highest
lowest address
address
®
Quark
October 2013
Order Number: 329679-001US
BHE#
0
0
11
h3
lb
mw †
hb †
lb
mlb ‡
mhb ‡
hb ‡
lb
hb