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System BIOS
As a part of the boot process, the BSP wakes each AP. When awakened, an AP programs its
memory type range registers (MTRRs) to be identical to those of the BSP. All APs execute a
halt instruction with their local interrupts disabled. If the BSP determines that an AP exists that
is a lower-featured processor or that has a lower value returned by the CPUID function, the BSP
switches to the lowest-featured processor in the server. The system management mode (SMM)
handler expects all processors to respond to a system management interrupt (SMI).
3.2.3
Mixed Processor Steppings
For optimum performance, only identical processors should be installed. Processor stepping
within a common processor family can be mixed as long as it is listed in the processor
specification updates published by Intel Corporation. The BIOS does not check for mixed
processor steppings. See the Intel
processor steppings. See also Table 4 .
3.2.4
Mixed Processor Families
Processor families cannot be mixed. If this condition is detected, an error is reported to the
BMC. See Table 4.
3.2.5
Mixed Processor System Bus Speeds
Processors with different system bus speeds cannot be mixed. If this condition is detected, an
error is reported to the BMC. See Table 4 for details.
3.2.6
Mixed Processor Cache Sizes
If the installed processors have mixed cache sizes, an error is reported to the BMC. The size of
all cache levels must match between all installed processors. See Table 4.
3.2.7
Microcode Update
If the system BIOS detects a processor for which a microcode update is not available, the BIOS
reports an error to the BMC. See Table 4.
IA-32 processors can correct specific errata by loading an Intel-supplied data block, known as a
microcode update. The BIOS stores the update in non-volatile memory and loads it into each
processor during POST. The BIOS allows a number of microcode updates to be stored in the
flash. This is limited by the amount of free space available.
3.2.8
Processor Cache
The BIOS enables all levels of processor cache as early as possible during POST. There are no
user options to modify the cache configuration, size, or policies. All detected cache sizes are
reported in the SMBIOS Type 7 structures. The largest and highest-level cache detected is
reported in BIOS Setup.
3.2.9
Mixed Processor Configuration
The following table describes mixed processor conditions and actions for all Intel
and systems that use the Intel
26
Intel® 5000 Series Chipsets Server Board Family Datasheet
®
®
Xeon
Processor Specification Update for supported mixed
®
5000 Series Chipset. Errors fall into one of two categories:
Intel order number D38960-004
®
server boards
Revision 1.1
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