Configuring Tl Port Alpa Caches; Configuring Buffer-To-Buffer Credits; Configuring Performance Buffers - Cisco DS-C9216I-K9 Configuration Manual

Configuring Fibre Channel Interfaces
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Configuring TL Port ALPA Caches

While TL ports cannot be automatically configured, you can manually configure entries in arbitrated
loop physical address (ALPA) caches. Generally, ALPA cache entries are automatically populated when
an ALPA is assigned to a device. Each device is identified by its port world wide name (pWWN). When
a device is allocated an ALPA, an entry for that device is automatically created in the ALPA cache.
A cache contains entries for recently allocated ALPA values. These caches are maintained on various TL
ports. If a device has an ALPA, the SAN-OS software attempts to allocate the same ALPA to the device
each time. The ALPA cache is maintained in persistent storage and saves information across switch
reboots. The maximum cache size is 1000 entries. If the cache is full, and a new ALPA is allocated, the
SAN-OS software discards an inactive cache entry (if available) to make space for the new entry.

Configuring Buffer-to-Buffer Credits

Buffer-to-buffer credits (BB_credits) are a flow control mechanism to ensure that FC switches do not
run out of buffers, since switches must not drop frames. Buffer Credits are negotiated on a per-hop basis.
The receive BB_credit (rxbbcredit) value may be configured for each FC interface. In most cases, you
don't need to modify the default configuration.
The receive BB_credit values depend on the module type and the port mode:
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In the Cisco MDS 9100 Series, the left most groups of ports outlined in white (4 ports in the 9120 switch
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and 8 ports in the 9140 switch) are full line rate like the 16-port switching module. The other ports (16
ports in the 9120 switch and 32 ports in the 9140 switch) are host-optimized like the 32-port switching
module. Each group of 4 host-optimized ports have the same rules as for the 32-port switching module.

Configuring Performance Buffers

Regardless of the configured Rx BB_credit value, additional buffers, called performance buffers,
improve switch port performance. Instead of relying on the built-in switch algorithm, you can manually
configure the performance buffer value for specific applications (for example, forwarding frames over
FCIP interfaces).
For each physical Fibre Channel interface in any switch in the Cisco MDS 9000 Family, you can specify
the amount of performance buffers allocated in addition to the configured receive BB_credit value.
The default performance buffer value is 0. If you use the Default option, the built-in algorithm is used.
If you do not specify this command, the Default option is automatically used.
Cisco MDS 9000 Fabric Manager Switch Configuration Guide
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In the Cisco MDS 9100 Series, the left most groups of ports outlined in white (4 ports in the 9120
switch and 8 ports in the 9140 switch) are full line rate like the 16-port switching module. The other
ports (16 ports in the 9120 switch and 32 ports in the 9140 switch) are host-optimized like the
32-port switching module. Each group of 4 host-optimized ports have the same rules as for the
32-port switching module.
16-port switching modules and full rate ports—The default value is 16 for the Fx mode and 255 for
E or TE modes. The maximum value is 255 in all modes. This value can be changed as required.
32-port switching modules and host-optimized ports—The default value is 12 for the Fx, E, and TE
modes. These values cannot be changed.
Chapter 12 Configuring Interfaces
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