Capture Mode Operation - Oki ML63611 User Manual

ML63611 User's Manual
Chapter 7 Timers (TIMER)

7.4.6 Capture Mode Operation

Timer 0 and timer 1 can be used as capture mode timers.
In a capture mode, a change in the capture input (PB.0/TM0CAP, PB.1/TM1CAP) level during operation of the
timer counter register triggers loading of the value of the timer counter register into the timer data register.
Methods to set the capture mode for each timer are listed below.
• Timer 0: Set TM0ECAP (bit 1 of TM0CON0) to "1", and set FMEAS0 (bit 2 of TM0CON0) to "0".
• Timer 1: Set TM1ECAP (bit 1 of TM1CON0) to "1".
In the capture mode, reloading the timer data register data into the timer counter register is inhibited, and when the
timer counter register overflows, counting is restarted from 00H.
When a capture occurs, the capture flags (TM0CAP, TM1CAP) of the timer status registers (TM0STAT,
TM1STAT) are set to "1". Additional captures are disabled while the capture flags are "1". The capture flags are
assigned to bit 0 of the timer status registers, and are automatically cleared to "0" when the timer status registers
are read.
If both the TM1CL1 and TM1CL0 bits of the timer 1 control register 1 (TM1CON1) are set to "1" and timer 0
overflow is selected as the clock, the 16-bit capture mode will be set. In this case, the PB.0/TM0CAP pin is the
capture trigger input.
Figure 7-8 shows the timer 0 capture mode timing for pulse width measurement.
TM0CH, TM0CL
TM0DH, TM0DL
TM0RUN
TM0ECAP
TM0INT
PB.0/TM0CAP input
TM0CAP
XI0INT
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
←
F0H
50H
↓
00H 50H F0H
→
→
←
t1
Figure 7-8 Capture Mode Timing
7 – 18
60H
60H
t2 t3
OPTION B (D): 1.5 V (3.0 V), With regulator
E0H
E0H
←
circuit for LCD bias