Table of Contents
Advertisement
16.3.2 Counter A/B Reference Mode
The conversion operation of the A/D converter is performed by one of the following two modes.
• Counter A Reference Mode (SADI bit of ADCON0 = 0)
This is the mode to set gate time by the system clock (CLK) and Counter A, to count the RC oscillation clock
(OSCCLK) by Counter B with the gate time and to output contents of Counter B as a digital value.
The digital value is proportional to the RC oscillation frequency.
• Counter B Reference Mode (SADI bit of ADCON0 = 1)
This is the mode to set gate time by the RC oscillation clock (OSCCLK) and Counter B, to count the system
clock (CLK) by Counter A with the gate time and to output contents of Counter A as a digital value.
The digital value is inversely proportional to the RC oscillation frequency.
(1) Operation of Counter A Reference Mode
Figure 16-6 shows the operating timing of Counter A reference mode.
Counter A reference mode is performed by the following procedure: (refer to Figure 16-6)
Subtract "nA0" (the count value) from the maximum value +1 (80,000) and set that value to Counter A
(CNTA4 to 0). Here, the product of the count value, "nA0", and the period of CLK indicates the gate
time.
Counter A ← (80,000 – nA0)
Clear Counter B (CNTB3 to 0) to 0000H.
Counter B ← 0000H
Set the bits OM3 to OM0 of ADCON1 to a necessary oscillation mode (refer to Table 16-1).
Set the internal power supply as the power supply voltage by first setting the halver circuit to "turned
OFF" (set bit 0 of VHCON to "0") and then writing "4H" to ADCON0 (STV = 1). In the OPTION A
and OPTION B, the setting of VHCON is not required.
Write ADCON0 to "5H" (STV =1, SADI = 0, EADC = 1) after waiting for about 120 µs.
!
Note:
The order of
to
After setting STV (bit 2 of ADCON0) to "1", wait for about 120 µs and then set EADC to "1". In the OPTION A and
OPTION B, the setting of VHCON is not required.
By , A/D conversion starts.
Counter A starts counting the system clock (CLK) when EADC is set to "1" and the CRON signal that
synchronizes with the falling of the system clock is set to "1". When Counter A overflows, the EADC bit is
automatically reset ( ) and the counting is finished. At the same time, the A/D converter interrupt request
signal (ADINT) becomes "1" to generate the A/D converter interrupt request ( ).
When the CRON signal is set to "1", the RC oscillation is started and Counter B starts counting the RC
oscillation clock (OSCCLK). When Counter A overflows and the EADC bit is automatically reset, the
counting of counter B is finished.
The last count value of "nB0" at Counter B is the count value of OSCCLK during the gate time
"nA0•t
" and is expressed by
SYSCLK
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
is arbitrary.
nB0 ≅ nA0 •
Chapter 16 A/D Converter (ADC)
t
∝ f
SYSCLK
OSCCLK
t
OSCCLK
16 – 7
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
circuit for LCD bias
Advertisement
Table of Contents
