Operation Of The Option D Power Supply Circuit - Oki ML63611 User Manual

ML63611 User's Manual
Chapter 15 Power Supply Circuit (POWER)

15.3.8 Operation of the OPTION D Power Supply Circuit

The output voltage (1/2 V
V/R2, and V/R3) of the OPTION D. The output voltages of the voltage regulator circuits are used as the internal
logic power supply (V
reference voltage (V
power supply of the high-speed clock generator circuit.
The software setting should be made so that the output voltage of the halver circuit is supplied to the different
voltage regulator circuits during normal load, and the battery voltage is directly supplied to the different voltage
regulator circuits during heavy load.
During normal load (V
during heavy load (V
circuit is not being used, the battery voltage will be supplied directly to the different voltage regulator circuits.
By setting the judgment threshold voltage of the BLD function to 2.4 V, it is possible to detect the battery voltage
during heavy load.
The output voltage of the voltage regulator V/R1 is supplied as the power supply (VH) for the internal logic
circuits during low-speed clock operation. Further, during high-speed clock operation, it is possible to directly
connect the battery voltage in the hardware to the power supply by first setting VH to "0" and then setting
ENOSC (bit 1 of FCON) to "1".
The output voltages of the voltage regulator circuits V/R2 and V/R3 are always supplied respectively as the power
supply voltage (V
XT
generator circuit.
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
) of the halver circuit is supplied to the different voltage regulator circuits (V/R1,
DD
), the power supply voltage (V
CH
) for LCD bias generator circuit. Further, the battery voltage is connected directly to the
DD1
= 2.4 to 3.6 V), use the halver circuit by setting VH (bit 0 of VHCON) to "1", and
DD
= less than 2.4 V), disable the halver circuit by setting VH to "0". When the halver
DD
) for the low-speed clock generator circuit and the reference voltage (V
) for the low-speed clock generator circuit, and the
XT
15 – 10
OPTION B (D): 1.5 V (3.0 V), With regulator
) for the LCD bias
DD1
circuit for LCD bias