Port E.3 External Interrupt Function (External Interrupt 2) - Oki ML63611 User Manual

10.7.3 Port E.3 External Interrupt Function (External Interrupt 2)

Port E.3 has external interrupt 2 allocated as secondary function.
External interrupt generation for PE.3 is triggered by the falling edge of the 128 Hz or 4 kHz time base counter,
which is the sampling clock.
After the port level changes, the interrupt request signal (XI2INT) is output, and the interrupt request flag (QXI2)
is set. The maximum delay for this sequence is one cycle of the sampling clock (128 Hz or 4 kHz).
The interrupt start address for external interrupt 2 is 0018H.
Figure 10-16 shows the equivalent circuit for external interrupt 2 control.
PE.3
128 Hz
4 kHz
PEMOD
PEF
Figure 10-16 External Interrupt 2 Control Equivalent Circuit
Figure 10-17 shows the external interrupt 2 generation timing.
128 Hz or
4 kHz
PE.3
XI2INT
QXI2
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
Level change
detect circuit
Figure 10-17 External Interrupt 2 Generation Timing
Chapter 10 Ports (INPUT, I/O PORT)
IRQ1
IE1.0
IRQ1.0
XI2INT
QXI2
10 – 31
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
IE1
to interrupt priority
encoder
EXI2
circuit for LCD bias