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Oki ML63326 User Manual

Cmos 4-bit microcontroller
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ML63326
User's Manual
CMOS 4-bit microcontroller
Preliminary
SECOND EDITION
ISSUE DATE: Sep. 1999
PEUL63326-02

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Summary of Contents for Oki ML63326

  • Page 1 ¡ ML63326 User's Manual CMOS 4-bit microcontroller Preliminary SECOND EDITION ISSUE DATE: Sep. 1999 PEUL63326-02...
  • Page 2 Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration...
  • Page 4 Preface This manual describes the hardware of Oki's original CMOS 4-bit microcontroller ML63326. Refer to the "nX-4/250 Core Instruction Manual" for details of the 4-bit CPU core nX-4/250 which is built in the ML63326. The manuals related to the ML63326 are shown below.
  • Page 5 Notation Classification Notation Description n Numeric value xxh, xxH Represents a hexadecimal number. Represents a binary number. n Unit word, W 1 word = 16 bits byte, B 1 byte = 2 nibbles = 8 bits nibble, N 1 nibble = 4 bits mega-, M kilo-, K = 1024...

  • Page 6: Table Of Contents

    Table of Contents Chapter 1 Overview 1.1 Overview ......................1-1 1.2 Features ......................1-1 1.3 Function List ....................1-5 1.4 Block Diagram ....................1-6 1.5 Pin Configuration ................... 1-7 1.6 Pin Descriptions ..................... 1-11 1.6.1 Descriptions of the Basic Pin Functions ..........1-11 1.6.2 Descriptions of the Secondary Pin Functions ........
  • Page 7 Chapter 3 CPU Control Functions 3.1 Overview ......................3-1 3.2 System Reset Mode (RST) ................3-2 3.2.1 Transfer to and State of System Reset Mode ........3-2 3.3 Halt Mode ...................... 3-3 3.3.1 Transfer to and State of Halt Mode ............ 3-3 3.3.2 Halt Mode Release ................
  • Page 8 Chapter 7 Timers (TIMER) 7.1 Overview ......................7-1 7.2 Timer Configuration ..................7-1 7.3 Timer Registers....................7-3 7.4 Timer Operation ..................... 7-14 7.4.1 Timer Clock ..................7-14 7.4.2 Timer Data Registers ................7-14 7.4.3 Timer Counter Registers ..............7-14 7.4.4 Timer Interrupt Requests and Overflow Flags ........7-15 7.4.5 Auto-Reload Mode Operation .............
  • Page 9 Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.1 Overview ......................10-1 10.2 Ports List ......................10-1 10.3 Port 0 (P0.0–P0.3) ..................10-2 10.3.1 Port 0 Configuration ................10-2 10.3.2 Port 0 Registers ................10-2 10.3.3 Port 0 External Interrupt Functions (External Interrupt 5) ....10-5 10.4 Ports 4–7 (P4.0–P4.3, P5.0–P5.3, P6.0–P6.3, P7.0–P7.3) ......
  • Page 10 Chapter 13 Voice Synthesis 13.1 Overview ......................13-1 13.2 Voice Synthesis Section Configuration ............13-1 13.3 Registers Related to the Voice Synthesis Section ......... 13-3 13.4 Voice ROM..................... 13-8 13.4.1 Voice ROM Configuration ..............13-8 13.4.2 Creation of Voice ROM Store Data ..........13-9 13.5 Voice Synthesis Section Clock Input Frequency ...........
  • Page 11 Chapter 16 Battery Low Detect Circuit (BLD) 16.1 Overview ......................16-1 16.2 Battery Low Detect Circuit Configuration ............16-1 16.3 Judgment Voltage ..................16-2 16.4 Battery Low Detect Circuit Register ............... 16-2 16.5 Battery Low Detect Circuit Operation ............16-3 Chapter 17 Power Supply Circuit (POWER) 17.1 Overview ......................
  • Page 12 Chapter 1 Overview Chapter 2 CPU and Memory Spaces Chapter 3 CPU Control Functions Chapter 4 Interrupt (INT326) Chapter 5 Clock Generator Circuit (OSC) Chapter 6 Time Base Counter (TBC) Chapter 7 Timers (TIMER) Chapter 8 100 Hz Timer Counter (100HzTC) Chapter 9 Watchdog Timer (WDT) Chapter 10 Ports (INPUT, OUTPUT, I/O PORT)

  • Page 14: Overview

    Chapter 1 Overview...

  • Page 16: Features

    The ML63326 is a 4-bit microcontroller with built-in voice synthesis section and 1024- segment dot matrix LCD driver. The ML63326 is ideal for applications such as game machines, toys, and clocks, that have LCD displays and synthesized voice outputs. The ML63326 is a mask ROM product belonging to the M633xx series of the OLMS-63K family with Oki's original nX-4/250 CPU core.
  • Page 17 ML63326 User's Manual Chapter 1 Overview h. Stack level Call stack level Register stack level i. Ports • Input ports: Selectable as input with pull-up resistor, input with pull-down resistor or high impedance input. Output ports: Selectable as P-channel open drain output/N-channel open drain output/CMOS output/high-impedance output.
  • Page 18 ML63326 User's Manual Chapter 1 Overview k. Melody output (MELODY63K) • Melody frequency: 529 Hz to 2979 Hz • Tone length: 63 varieties • Tempo: 15 varieties • Melody data: Stored in program memory • Buzzer driver signal output: 4 kHz l.
  • Page 19 ML63326 User's Manual Chapter 1 Overview r. Shipping products Package Product • Chip (159 pads) ML63326-xxx • 176-pin flat package (176LQFP) ML63326-xxxTC LQFP176-P-2424-0.50-BK xxx indicates the ROM code number. s. Operating temperature • –20 to +70°C t. Power supply voltage •...

  • Page 20: Function List

    ML63326 User's Manual Chapter 1 Overview 1.3 Function List Table 1-1 shows a list of the ML63326 functions. The solid black circles within the chart indicate that the product has the particular function. Table 1-1 Function List Function Symbol ML63326 Reference page Æ2-7...

  • Page 21: Block Diagram

    ML63326 User's Manual Chapter 1 Overview 1.4 Block Diagram Figure 1-1 is the block diagram of the ML63326. Asterisks (*) indicate the secondary function of each port. Signal names enclosed by chain lines ( ) indicate interface signals of the V power supply system.

  • Page 22: Pin Configuration

    ML63326 User's Manual Chapter 1 Overview 1.5 Pin Configuration The ML63326 pin configuration, chip pin configuration, and pad coordinates are shown in Figures 1-2, 1-3, and Table 1-2, respectively. NC (not connected) indicates an unused pin that is left unconnected (open).
  • Page 23 : 100 mm ¥ 100 mm • Pad hole size : 110 mm ¥ 110 mm • Pad size : 140 mm • Minimum pad pitch Note: The chip substrate voltage is V Figure 1-3 ML63326 Chip Pin Configuration (Top View)
  • Page 24 ML63326 User's Manual Chapter 1 Overview Table 1-2 ML63326 Pad Coordinates Center of chip: x = 0, y = 0 Pad No. Pad name X (mm) Y (mm) Pad No. Pad name X (mm) Y (mm) DACOUT –2582 –3039 SEG24 2766 –2617...
  • Page 25 ML63326 User's Manual Chapter 1 Overview Table 1-2 ML63326 Pad Coordinates (continued) Center of chip: x = 0, y = 0 Pad No. Pad name X (mm) Y (mm) Pad No. Pad name X (mm) Y (mm) COM9 2609 3039 PE.0...

  • Page 26: Pin Descriptions

    1.6.1 Descriptions of the Basic Pin Functions The basic functions of the ML63326 pins are listed in Table 1-3. Use of a slash ("/") in a pin name indicates that the pin has a secondary function. Refer to section 1.6.2, "Descriptions of the Secondary Pin Functions."...
  • Page 27 ML63326 User's Manual Chapter 1 Overview Table 1-4 Pin Description (Basic Functions) (continued) Pin No. Pad No. Classification Pin name Function Melody output pin (positive phase) Melody Melody output pin (reversed phase) DACOUT Voice output pin (12-bit DAC output) AOUT...
  • Page 28 ML63326 User's Manual Chapter 1 Overview Table 1-3 Pin Description (Basic Functions) (continued) Classification Pin name Pin No. Pad No. Function 4-bit I/O port: P9.0 During the input mode, each bit can be selected as the following. • Input with pull-up resistor •...
  • Page 29 ML63326 User's Manual Chapter 1 Overview Table 1-3 Pin Description (Basic Functions) (continued) Classification Pin name Pin No. Pad No. Function LCD common signal output pins (COM1 to COM16) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11...
  • Page 30 ML63326 User's Manual Chapter 1 Overview Table 1-3 Pin Description (Basic Functions) (continued) Classification Pin name Pin No. Pad No. Function LCD segment signal output pins (SEG27 to SEG63) SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37...

  • Page 31: Descriptions Of The Secondary Pin Functions

    ML63326 User's Manual Chapter 1 Overview 1.6.2 Descriptions of the Secondary Pin Functions The secondary functions of the ML63326 pins are listed in Table 1-4. Table 1-4 Pin Description (Secondary Functions) Classification Pin name Pin No. Pad No. Function PB.0/INT0 External interrupt 0 input pins: PB.1/INT0...
  • Page 32 ML63326 User's Manual Chapter 1 Overview Table 1-4 Pin Description (Secondary Functions) (continued) Classification Pin name Pin No. Pad No. Function P4.0/A0 P4, P5, P6, P7 secondary functions: P4.1/A1 Address bus signals for external memory access. P4.2/A2 P4.3/A3 P5.0/A4 P5.1/A5 P5.2/A6...

  • Page 33: Unused Pin Processing

    ML63326 User's Manual Chapter 1 Overview 1.6.3 Unused Pin Processing Table 1-5 lists the handling of unused pins. Table 1-5 Unused Pin Handling Recommended pin handling OSC0, OSC1 Open CB1, CB2 Open Open C1, C2 Open Open TST1, TST2, VTEST Open or V P0.0–P0.3...

  • Page 34: Basic Timing

    ML63326 User's Manual Chapter 1 Overview 1.7 Basic Timing 1.7.1 Basic Timing of CPU Operation The system clock (CLK) uses the low-speed oscillation clock using the XT0 and XT1 pins or the high-speed oscillation clock using the OSC0 and OSC1 pins (1/2 frequency waveform when a crystal oscillator is used, no frequency division when an RC oscillator is used).The...
  • Page 35 ML63326 User's Manual Chapter 1 Overview Output instruction Input instruction Instruction (example) MOV obj,(data A) MOV A,obj Output pin (data A) Input pin (data B) Accumulator (data B) Figure 1-5 Port I/O Basic Timing Note: Regarding input signals "0" will be captured in the internal register if a "L" level is input to the input pin even once (q of Figure 1-6) during the data capture interval.

  • Page 36: Interrupt Basic Timing

    ML63326 User's Manual Chapter 1 Overview 1.7.3 Interrupt Basic Timing Figure 1-7 shows the basic interrupt timing. As shown in the figure, when an interrupt factor is generated, the interrupt factor is sampled at the falling edge of CLK and an interrupt request (IRQ) is set at the first half of S1.

  • Page 37: Overview

    ML63326 User's Manual Chapter 1 Overview 1-22...
  • Page 38 Chapter 2 CPU and Memory Spaces...

  • Page 40: Registers

    Chapter 2 CPU and Memory Spaces 2.1 Overview The ML63326 is equipped with an Oki’s original CPU core nX-4/250. The instruction set of the nX-4/250 core consists of 439 types of instructions. The memory space consists of a 16-bit wide program memory space, a 4-bit wide data memory space, and an 8-bit wide memory space for storing voice synthesis and character data.

  • Page 41: Zero Flag (Z)

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.2.2.2 Zero Flag (Z) The zero flag (Z) is a 1-bit flag that is set to "1" when the contents of the accumulator (A) are loaded with "0H". The zero flag is set to "0" when the contents of the accumulator (A) are loaded with a value other than "0H".

  • Page 42: Current Bank Register (Cbr), Extra Bank Register (Ebr), Hl Register (Hl), Xy Register (Xy)

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR), HL Register (HL), XY Register (XY) The CBR, EBR, HL, and XY registers are used for indirect addressing of data memory. The CBR and EBR registers indicate the data memory bank. The HL and XY registers indicate addresses in the bank.

  • Page 43: Program Counter (Pc)

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.2.5 Program Counter (PC) The program counter (PC) is a counter with 16 valid bits that specifies the program memory space. 2.2.6 RA Registers (RA3, RA2, RA1, RA0) The RA registers are used for indirect program memory addressing (ROM table reference instructions).

  • Page 44: Stack Pointer (Sp) And Call Stack

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.2.7 Stack Pointer (SP) and Call Stack The stack pointer (SP) is a pointer that indicates the call stack address where the program counter is saved when a subroutine call or interrupt occurs.

  • Page 45: Register Stack Pointer (Rsp) And Register Stack

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.2.8 Register Stack Pointer (RSP) and Register Stack The register stack pointer (RSP) is a pointer that indicates the register stack address for saving various registers. RSP is a 4-bit up/down counter that is incremented during stack saves (execution of PUSH instructions) and is decremented during stack restores (execution of POP instructions).

  • Page 46: Memory Spaces

    The melody data defines the tone, tone length, and end tone used in the melody circuit (MELODY63K) of the ML63326. After an MSA instruction specifies the starting address, the melody data is automatically transferred to the melody circuit when a melody data interrupt occurs.

  • Page 47: Data Memory Space

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.3.2 Data Memory Space The data memory space contains data RAM and special function registers (SFRs). The data memory consists of 8 banks. One bank unit is 256 nibbles. BANK 0 is allocated as a SFR area, BANK 1 as the LCD display register, and BANK 2 and the following BANKS are data RAM.

  • Page 48: Memory Space For Voice Synthesis And Character Data

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.3.3 Memory Space for Voice Synthesis and Character Data The memory space for voice synthesis and character data is configured by a mask ROM that stores the voice data necessary for the built-in voice synthesis function and the character data used for the LCD display.

  • Page 49: External Memory Space

    ML63326 User's Manual Chapter 2 CPU and Memory Spaces 2.3.4 External Memory Space The external memory space is one for storing the voice data necessary for the built-in voice synthesis function and the character data used for the LCD display, and is accessed via a port.

  • Page 50: Chapter 3 Cpu Control Functions

    Chapter 3 CPU Control Functions...

  • Page 52: Overview

    ML63326 User's Manual Chapter 3 CPU Control Functions Chapter 3 CPU Control Functions 3.1 Overview Operating states, including system reset, are classified as follows. • Normal operation mode • System reset mode • Halt mode Figure 3-1 shows the CPU operating state transition diagram.

  • Page 53: System Reset Mode (Rst)

    ML63326 User's Manual Chapter 3 CPU Control Functions 3.2 System Reset Mode (RST) 3.2.1 Transfer to and State of System Reset Mode The following three factors cause a transfer to the system reset mode. • Setting the RESET pin to a "H" level (for 1 ms or more) •...

  • Page 54: Halt Mode

    ML63326 User's Manual Chapter 3 CPU Control Functions 3.3 Halt Mode 3.3.1 Transfer to and State of Halt Mode Transfer to the halt mode is performed by the software when a HALT instruction is executed. When a HALT instruction is executed, the CPU enters the HALT mode at the S2 state of the HALT instruction.

  • Page 55: Halt Mode Release

    ML63326 User's Manual Chapter 3 CPU Control Functions 3.3.2 Halt Mode Release The following two methods are available to release the halt mode. • Release by interrupt generation (transfer to normal operation mode) • Release by RESET pin (transfer to system reset mode) 3.3.2.1 Release of Halt Mode by Interrupt...

  • Page 56: Melody Data Interrupt And Halt Mode Release

    ML63326 User's Manual Chapter 3 CPU Control Functions 3.3.3 Melody Data Interrupt and Halt Mode Release The halt mode is not released by a melody data interrupt. The melody data interrupt is different from a conventional interrupt in that the melody data interrupt is a hardware processing interrupt used for transfer of melody data to the melody circuit.
  • Page 57 ML63326 User's Manual Chapter 3 CPU Control Functions...

  • Page 58: Chapter 4 Interrupt (Int326)

    Chapter 4 Interrupt (INT326)

  • Page 60: Overview

    Chapter 4 Interrupt (INT326) 4.1 Overview The ML63326 supports 17 interrupt factors: 4 external interrupts and 13 internal interrupts. With the exception of the watchdog timer interrupt, interrupt enable/disable is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE0 to IE4).
  • Page 61 ETM3 IRQ3 IE3.2 IRQ3.2 QSFT SFTINT ESFT IE3.3 IRQ3.3 T10HzINT Q10Hz E10Hz IRQ4 IE4.0 IRQ4.0 Q32Hz 32HzINT E32Hz IRQ4.1 IE4.1 E16Hz 16HzINT Q16Hz IE4.2 IRQ4.2 Q4Hz 4HzINT E4Hz IRQ4.3 IE4.3 2HzINT Q2Hz E2Hz Figure 4-1 ML63326 Interrupt Control Equivalent Circuit...

  • Page 62: Interrupt Registers

    ML63326 User's Manual Chapter 4 Interrupt (INT326) 4.2 Interrupt Registers The following three types of registers are used to control interrupts. (1) Master interrupt enable register (MIEF) (2) Interrupt enable registers (IE0 to IE4) (3) Interrupt request registers (IRQ0 to IRQ4) These registers are described below.
  • Page 63 ML63326 User's Manual Chapter 4 Interrupt (INT326) (2) Interrupt enable registers (IE0 to IE4) IE0, IE1, IE2, IE3, and IE4 are registers that consist of 4 bits each. A logical AND of the corresponding bits of an interrupt enable register (IE0 to IE4) and an interrupt request register (IRQ0 to IRQ4) determines whether or not each interrupt request is issued to the CPU.
  • Page 64 ML63326 User's Manual Chapter 4 Interrupt (INT326) bit 3 bit 2 bit 1 bit 0 IE2 (052H) ETM3 ETM2 ETM1 ETM0 (R/W) Timer 3 interrupt enable flag 0: Disable (initial value) 1: Enable Timer 2 interrupt enable flag 0: Disable (initial value)
  • Page 65 ML63326 User's Manual Chapter 4 Interrupt (INT326) (3) Interrupt request registers (IRQ0 to IRQ4) IRQ0, IRQ1, IRQ2, IRQ3 and IRQ4 are registers that consist of 4 bits each. When an interrupt request is generated, the corresponding bit of the interrupt request register is set to "1"...
  • Page 66 ML63326 User's Manual Chapter 4 Interrupt (INT326) bit 1: QMD (reQuest Melody Driver) Melody end interrupt request flag. Melody end interrupts are generated when the melody driver outputs the end note data (END bit = "1"). bit 0: QWDT (reQuest WatchDog Timer) Watchdog timer interrupt request flag.
  • Page 67 ML63326 User's Manual Chapter 4 Interrupt (INT326) bit 3 bit 2 bit 1 bit 0 IRQ2 (057H) QTM3 QTM2 QTM1 QTM0 (R/W) Timer 3 interrupt request flag 0: No request (initial value) 1: Request Timer 2 interrupt request flag 0: No request (initial value)
  • Page 68 ML63326 User's Manual Chapter 4 Interrupt (INT326) bit 3 bit 2 bit 1 bit 0 IRQ4 (059H) Q2Hz Q4Hz Q16Hz Q32Hz (R/W) 2 Hz interrupt request flag 0: No request (initial value) 1: Request 4 Hz interrupt request flag 0: No request (initial value)

  • Page 69: Interrupt Sequence

    ML63326 User's Manual Chapter 4 Interrupt (INT326) 4.3 Interrupt Sequence 4.3.1 Interrupt Processing While MIE is "1", operation transfers to interrupt processing when individual interrupt factors are generated. The watchdog timer interrupt is non-maskable and regardless of the MIE flag status, operation will shift to interrupt processing when the watchdog timer interrupt factor is generated.

  • Page 70: Return From An Interrupt Routine

    ML63326 User's Manual Chapter 4 Interrupt (INT326) 4.3.2 Return from an Interrupt Routine Return from a watchdog timer interrupt routine is performed with an "RTNMI" instruction. Return from all other interrupt routines is performed with an "RTI" instruction. Execution of "RTI" and "RTNMI" instructions both require 1 machine cycle.
  • Page 71 ML63326 User's Manual Chapter 4 Interrupt (INT326) 4-12...

  • Page 72: Chapter 5 Clock Generator Circuit (Osc)

    Chapter 5 Clock Generator Circuit (OSC)

  • Page 74: Overview

    ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) Chapter 5 Clock Generator Circuit (OSC) 5.1 Overview The clock generator circuit (OSC) consists of a low-speed clock generator circuit, a high- speed clock generator circuit and a clock controller unit. The clock generator circuit generates the system clock (CLK), time base clock (TBCCLK) and the high-speed clock (HSCLK).

  • Page 75: Low-Speed Clock Generator Circuit

    ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) 5.3 Low-Speed Clock Generator Circuit The low-speed clock generator circuit has two modes that are selected by the mask option, the RC oscillation mode and crystal oscillation mode. The oscillation frequency is 30 to 80 kHz.
  • Page 76 ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) Table 5-1 lists typical values of oscillation frequency when the low-speed side RC oscillation mode is selected. Table 5-2 shows an example external component to be attached when the low-speed side crystal oscillation mode is selected.

  • Page 77: High-Speed Clock Generator Circuit

    ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) 5.4 High-Speed Clock Generator Circuit The high-speed clock generator circuit has two modes, the RC oscillation mode and crystal oscillation mode. Oscillation modes are set by OSCSEL (bit 2 of FCON).
  • Page 78 ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) Table 5-3 lists typical values of oscillation frequency when the high-speed side RC oscillation mode is selected. Table 5-4 lists example external components to be attached when the high- speed side crystal oscillation mode is selected.

  • Page 79: System Clock Control

    ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) 5.5 System Clock Control The system clock is the basic operation clock of the CPU. The clock can be selected as follows with the CPUCLK (bit 0 of FCON) setting. •...

  • Page 80: Frequency Control Register (Fcon)

    ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) 5.6 Frequency Control Register (FCON) FCON is a special function register (SFR) that selects the system clock. bit 3 bit 2 bit 1 bit 0 FCON (062H) — OSCSEL ENOSC CPUCLK...

  • Page 81: System Clock Select Timing

    ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) 5.7 System Clock Select Timing After system reset, the system clock is TBCCLK. When high-speed operation is necessary, switch the system clock to HSCLK. A flowchart of system clock operation is shown below.
  • Page 82 ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) When ENOSC (bit 1 of FCON) is set to "1", the voltage doubler circuit that doubles V starts operating and outputs the power supply voltage (V ) for high speed oscillation. The oscillations are started in the mode set by OSCSEL.
  • Page 83 ML63326 User's Manual Chapter 5 Clock Generator Circuit (OSC) 5-10...

  • Page 84: Chapter 6 Time Base Counter (Tbc)

    Chapter 6 Time Base Counter (TBC)

  • Page 86: Overview

    ML63326 User's Manual Chapter 6 Time Base Counter (TBC) Chapter 6 Time Base Counter (TBC) 6.1 Overview The time base counter (TBC) is a 15-bit internal counter, which generates the clock supplied to internal peripheral functions. The TBC clock is a time base clock (TBCCLK).

  • Page 87: Time Base Counter Registers

    ML63326 User's Manual Chapter 6 Time Base Counter (TBC) 6.3 Time Base Counter Registers Time base counter register 0 (TBCR0), time base counter register 1 (TBCR1) These 4-bit special function registers (SFRs) are used to read the 1 to 8 Hz and 16 to 128 Hz outputs of the time base counter.

  • Page 88: Time Base Counter Operation

    ML63326 User's Manual Chapter 6 Time Base Counter (TBC) 6.4 Time Base Counter Operation After system reset the time base counter (TBC) begins to count up from 0000H. The count is incremented at the falling edge of the TBCCLK. TBC 32 Hz/16 Hz/4 Hz/2 Hz outputs are used as time base interrupts. At each output falling edge, four bits of interrupt request register 4 (IRQ4) are set to "1", namely bit 3 (Q32Hz), bit...
  • Page 89 Write TBCR0 Write TBCR1 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz second second –1/16 –1/256 Shows interrupt timing Figure 6-2 Interrupt Timing and Reset Timing by Writing "1" to TBCR0, TBCR1...

  • Page 90: Chapter 7 Timers (Timer)

    Chapter 7 Timers (TIMER)

  • Page 92: Overview

    Chapter 7 Timers (TIMER) 7.1 Overview The ML63326 has four internal 8-bit timers (0 to 3). Timers 0 and 1, or timers 2 and 3, can be used in tandem as a 16-bit timer. Timers 0 and 1 have three operation modes: auto-reload mode, capture mode and frequency measurement mode.
  • Page 93 ML63326 User's Manual Chapter 7 Timers (TIMER) Data bus TBCCLK overflow TM1CK HSCLK TM1INT Control TM1CL TM1CH PB.3/T13CK circuit TM0 overflow Capture Reload TM1CK Capture PB.1/TM1CAP TM1DL TM1DH PB.1/TM1OVF control circuit TM1CAP RESETS Figure 7-2 Timer 1 Configuration Data bus...

  • Page 94: Timer Registers

    ML63326 User's Manual Chapter 7 Timers (TIMER) 7.3 Timer Registers The following four registers are used for timer control. (1) Timer data registers (TM0DL, TM0DH, TM1DL, TM1DH, TM2DL, TM2DH, TM3DL, TM3DH) (2) Timer counter registers (TM0CL, TM0CH, TM1CL, TM1CH, TM2CL, TM2CH, TM3CL, TM3CH)
  • Page 95 ML63326 User's Manual Chapter 7 Timers (TIMER) Timer 2 Registers bit 3 bit 2 bit 1 bit 0 TM2DL (076H) T2D3 T2D2 T2D1 T2D0 (Timer 2 lower) (R/W) bit 3 bit 2 bit 1 bit 0 TM2DH (077H) T2D7 T2D6...
  • Page 96 ML63326 User's Manual Chapter 7 Timers (TIMER) Timer 1 Registers bit 3 bit 2 bit 1 bit 0 TM1CL (06EH) T1C3 T1C2 T1C1 T1C0 (Timer 1 lower) (R/W) bit 3 bit 2 bit 1 bit 0 TM1CH (06FH) T1C7 T1C6...
  • Page 97 ML63326 User's Manual Chapter 7 Timers (TIMER) (3) Timer control registers (TM0CON0, TM0CON1, TM1CON0, TM1CON1, TM2CON0, TM2CON1, TM3CON0, TM3CON1) • Timer control registers select the operation mode and clock for each timer. • At system reset, all valid bits are cleared to "0".
  • Page 98 ML63326 User's Manual Chapter 7 Timers (TIMER) bit 3 bit 2 bit 1 bit 0 TM0CON1 (071H) — — TM0CL1 TM0CL0 (R/W) Timer 0 clock select bit 1 bit 0 TBCCLK (initial value) HSCLK (high-speed clock) External clock Not used bit 1, 0: TM0CL1, TM0CL0 These bits select the timer 0 clock.
  • Page 99 ML63326 User's Manual Chapter 7 Timers (TIMER) Timer 1 Registers bit 3 bit 2 bit 1 bit 0 TM1CON0 (072H) — — TM1ECAP TM1RUN (R/W) Timer 1 mode select bit 1 bit 0 Auto-reload mode stop or 16-bit timer mode (initial value)
  • Page 100 ML63326 User's Manual Chapter 7 Timers (TIMER) Timer 2 Registers To use timer 3 in combination as a 16-bit timer, set timer 3 control registers TM3CON0 and TM3CON1. bit 3 bit 2 bit 1 bit 0 TM2CON0 (07EH) — FMEAS2 —...
  • Page 101 ML63326 User's Manual Chapter 7 Timers (TIMER) Timer 3 Registers bit 3 bit 2 bit 1 bit 0 TM3CON0 (080H) — — — TM3RUN (R/W) Timer 3 mode select Auto-reload mode stop or 16-bit timer mode (initial value) Auto-reload mode operation bit 0: TM3RUN This bit selects the timer 3 operation mode.
  • Page 102 ML63326 User's Manual Chapter 7 Timers (TIMER) (4) Timer status registers (TM0STAT, TM1STAT, TM2STAT, TM3STAT) • Timer status registers read the status of each timer. • At system reset, all valid bits are cleared to "0". Timer 0 Registers bit 3...
  • Page 103 ML63326 User's Manual Chapter 7 Timers (TIMER) bit 1: TM1CAP (TiMer1 CAPture) This bit indicates whether or not new capture data is present. When TM1CAP = "0": A value of "0" indicates that there has been no new capture data since system reset or since the last time TM1CAP was read.
  • Page 104 ML63326 User's Manual Chapter 7 Timers (TIMER) [Supplement] List of Timer Registers Timer 0 Registers Name Symbol Address Initial value Timer 0 data register L TM0DL 068H Timer 0 data register H TM0DH 069H Timer 0 counter register L TM0CL...

  • Page 105: Timer Operation

    ML63326 User's Manual Chapter 7 Timers (TIMER) 7.4 Timer Operation 7.4.1 Timer Clock The timer clock can be selected as TBCCLK (low-speed clock: 32.768 kHz), HSCLK (high- speed clock), or an external clock. By using timer 0 and timer 2 overflow signals as clocks for timer 1 and timer 3, respectively, the timers can be used in pairs as 16-bit timers.

  • Page 106: Timer Interrupt Requests And Overflow Flags

    ML63326 User's Manual Chapter 7 Timers (TIMER) 7.4.4 Timer Interrupt Requests and Overflow Flags Timers generate timer interrupt requests when the timer counter register overflows. The overflow flag toggles between "1" and "0" at each overflow. The output of the overflow flag of timers 0 and 1 can be output to secondary port functions PB.0/TM0OVF and PB.1/TM1OVF...

  • Page 107: Auto-Reload Mode Operation

    ML63326 User's Manual Chapter 7 Timers (TIMER) 7.4.5 Auto-Reload Mode Operation Timers 0 to 3 can be used as auto-reload mode timers. The setup method is as follows. • Timer 0: Set FMEAS0 (bit 2 of TM0CON0) to "0", and set TM0ECAP (bit 1 of TM0CON0) to "0".
  • Page 108 ML63326 User's Manual Chapter 7 Timers (TIMER) The operation procedures are as follows. q Set PB.1 to the output mode (TM1OVF) secondary function. w Write 534FH to the timer data and timer counter registers. TM1DH = TM1CH = 5H (bits 15–12) TM1DL = TM1CL = 3H (bits 11–8)

  • Page 109: Capture Mode Operation

    ML63326 User's Manual Chapter 7 Timers (TIMER) 7.4.6 Capture Mode Operation Timer 0 and timer 1 can be used as capture mode timers. In a capture operation, a change in the capture input (PB.0/TM0CAP, PB.1/TM1CAP) level during operation of the timer counter register triggers loading of the value of the timer counter register into the timer data register.
  • Page 110 ML63326 User's Manual Chapter 7 Timers (TIMER) The operation procedure is listed below. q Set PB.0/TM0CAP to input mode, and enable XI0INT and TM0INT. w Clear all bits of the timer counter registers and timer data registers to zero. e Set TM0CON0 to the capture mode, and set TM0RUN to "1" to begin upward counting.
  • Page 111 ML63326 User's Manual Chapter 7 Timers (TIMER) CAPT PB.0/TM0CAP input Timer clock TM0ECAP TM0CAP Figure 7-10 Capture Signal (CAPT) Generator Circuit Note: The maximum delay from a PB.0/TM0CAP input level change until capture is one cycle of the timer clock.

  • Page 112: Frequency Measurement Mode Operation

    ML63326 User's Manual Chapter 7 Timers (TIMER) 7.4.7 Frequency Measurement Mode Operation The frequency measurement mode is used to measure the frequency of the RC oscillator clock, which has wide product variation. Timers 0 and 1, and timers 2 and 3 can be used in the frequency measurement mode. These timers are set as follows for the frequency measurement mode: •...
  • Page 113 ML63326 User's Manual Chapter 7 Timers (TIMER) Assuming that the ceramic oscillation clock is exactly 2 MHz, value N1 read from the timer counter register is: N1 = 2000000 ¥ 437/32768 = 26672 (decimal) = 6380 (hexadecimal) = 0110 1000 0011 0000 (binary)
  • Page 114 ML63326 User's Manual Chapter 7 Timers (TIMER) Figure 7-12 illustrates the operation of timer 3 interrupt for an RC oscillator clock frequency of 600 kHz. FFFF FFC2 TM3CH TM3CL TM2CH TM2CL 0000 TM3DH, TM3DL FFC2 TM2DH, TM2DL TM3INT (9677 Hz) 0.10333 ms...
  • Page 115 ML63326 User's Manual Chapter 7 Timers (TIMER) 7-24...
  • Page 116 Chapter 8 100 Hz Timer Counter (100HzTC)

  • Page 118: Chapter 8 100 Hz Timer Counter (100Hztc)

    ML63326 User's Manual Chapter 8 100 Hz Timer Counter (100HzTC) Chapter 8 100 Hz Timer Counter (100HzTC) 8.1 Overview The 100 Hz timer counter has a circuit that divides the TBC6 output (512 Hz) of the time base counter to generate a 10 Hz interrupt. The 100 Hz timer consists of a 5/6-base counter and two decimal counters.

  • Page 119: 100 Hz Timer Counter Registers

    ML63326 User's Manual Chapter 8 100 Hz Timer Counter (100HzTC) 8.3 100 Hz Timer Counter Registers (1) 100 Hz timer counter control register (T100CON) This is a 4-bit special function register (SFR) controlling the 100 Hz timer counter. bit 3...

  • Page 120: 100 Hz Timer Counter Operation

    ML63326 User's Manual Chapter 8 100 Hz Timer Counter (100HzTC) 8.4 100 Hz Timer Counter Operation The 100 Hz timer counter begins counting when bit 0 (ECNT) of the 100 Hz timer counter control register (T100CON) is set to "1". The 512 Hz output of the time base counter is divided into 100 Hz by the 5/6-base counter.
  • Page 121 ML63326 User's Manual Chapter 8 100 Hz Timer Counter (100HzTC)

  • Page 122: Chapter 9 Watchdog Timer (Wdt)

    Chapter 9 Watchdog Timer (WDT)

  • Page 124: Overview

    ML63326 User's Manual Chapter 9 Watchdog Timer (WDT) Chapter 9 Watchdog Timer (WDT) 9.1 Overview The watchdog timer is a circuit to detect CPU malfunction. The WDT consists of a 9-bit watchdog timer counter (WTDC) counting the 256 Hz output of the TBC7 of the time base counter (TBC), and a watchdog timer control register (WDTCON) to start and clear WDTC.

  • Page 125: Watchdog Timer Control Register (Wdtcon)

    ML63326 User's Manual Chapter 9 Watchdog Timer (WDT) 9.3 Watchdog Timer Control Register (WDTCON) The watchdog timer control register (WDTCON) is a 4-bit write only special function register (SFR) used to start/clear the watchdog timer counter (WDTC). bit 3 bit 2...
  • Page 126 ML63326 User's Manual Chapter 9 Watchdog Timer (WDT) Figure 9-2 shows a flowchart of watchdog timer processing. WDT operation is stopped System reset Internal pointer "0" Write "5H" Internal pointer "0"Æ"1" to WDTCON Write "0AH" WDT operation is started to WDTCON Internal pointer "1"Æ...
  • Page 127 ML63326 User's Manual Chapter 9 Watchdog Timer (WDT) Figure 9-3 shows the timing chart for watchdog timer operation. Fault occurrence Ø System reset Data: WDTCON write signal Internal pointer Overflow Watchdog timer counter (WDTC) content 1.9 to 2.0 s Start...

  • Page 128: Chapter 10 Ports (Input, Output, I/O Port)

    Chapter 10 Ports (INPUT, OUTPUT, I/O PORT)

  • Page 130: Overview

    Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.1 Overview The ML63326 has one internal 4-bit input port, four internal 4-bit output ports, five internal 4- bit I/O ports, and one internal 2-bit I/O port. The V (interface power supply) pin supplies power to the ports.

  • Page 131: Port 0 (P0.0-P0.3)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.3 Port 0 (P0.0–P0.3) 10.3.1 Port 0 Configuration The ML63326 has Port 0, a 4-bit input-only port. Figure 10-1 shows the configuration of port 0. Data bus P0CON0 Pull-up/ P0CON1...
  • Page 132 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (2) Port Control Registers (P0CON0, P0CON1) Port 0 control registers 0/1 (P0CON0, P0CON1) are 4-bit special function registers (SFRs) that select pull-up or pull-down resistors and select the external interrupt sampling frequency of Port 0 secondary function.
  • Page 133 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (3) Port Interrupt Enable Register (P0IE) The port 0 interrupt enable register (P0IE) is a 4-bit special function register (SFR) that enables/disables individual bits when port 0 is used as an external interrupt.

  • Page 134: Port 0 External Interrupt Functions (External Interrupt 5)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.3.3 Port 0 External Interrupt Functions (External Interrupt 5) An external interrupt (external interrupt 5) is assigned to port 0 as a secondary function. Individual bits can be enabled/disabled for external interrupt 5.
  • Page 135 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 128 Hz or 4 kHz P0.0 P0.1 P0.2 P0.3 XI5INT QXI5 (a) When P0PUD = 0 128 Hz or 4 kHz P0.0 P0.1 P0.2 P0.3 XI5INT QXI5 (b) When P0PUD = 1...

  • Page 136: Ports 4-7 (P4.0-P4.3, P5.0-P5.3, P6.0-P6.3, P7.0-P7.3)

    Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.4 Ports 4–7 (P4.0–P4.3, P5.0–P5.3, P6.0–P6.3, P7.0–P7.3) The ML63326 has four 4-bit output ports: Port 4, Port 5, Port 6, and Port 7. 10.4.1 Port 4–7 Configuration The circuit configuration for ports 4, 5, 6, and 7 is shown in Figure 10-4.

  • Page 137: Port 4-7 Registers

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.4.2 Port 4–7 Registers (1) Port data registers (P4D, P5D, P6D, P7D) The port 4 data register (P4D), port 5 data register (P5D), port 6 data register (P6D) and port 7 data register (P7D) are 4-bit special function registers (SFRs) used to set the output values for the ports.
  • Page 138 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) At system reset the port data registers are set to "0". When data is written to a port data register, the actual pin change timing is at the rising edge of the system clock for state 2 of the write instruction.
  • Page 139 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (2) Port control registers (P4CON0, P4CON1, P5CON0, P5CON1, P6CON0, P6CON1, P7CON0, P7CON1) The port 4 control registers 0/1 (P4CON0, P4CON1), port 5 control registers 0/1 (P5CON0, P5CON1), port 6 control registers 0/1 (P6CON0, P6CON1) and port 7 control registers (P7CON0, P7CON1) are 4-bit special function registers (SFRs) used to select port output mode.
  • Page 140 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) • Port 5 bit 3 bit 2 bit 1 bit 0 P5CON0 (01CH) P51MD1 P51MD0 P50MD1 P50MD0 (R/W) Port 5.1 output mode select bit 3 bit 2 0 : CMOS output (initial value)
  • Page 141 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) • Port 6 bit 3 bit 2 bit 1 bit 0 P6CON0 (01EH) P61MD1 P61MD0 P60MD1 P60MD0 (R/W) Port 6.1 output mode select bit 3 bit 2 0 : CMOS output (initial value)
  • Page 142 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) • Port 7 bit 3 bit 2 bit 1 bit 0 P7CON0 (020H) P71MD1 P71MD0 P70MD1 P70MD0 (R/W) Port 7.1 output mode select bit 3 bit 2 0 : CMOS output (initial value)
  • Page 143 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (3) Port mode register (P47MOD) The port 4–7 mode register (P47MOD) is a 4-bit special function register (SFR) that enables the external memory address bus function, which is the secondary function of ports 4–7.

  • Page 144: Port 8, Port 9, Port A (P8.0, P8.1, P9.0-P9.3, Pa.0-Pa.3)

    Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.5 Port 8, Port 9, Port A (P8.0, P8.1, P9.0–P9.3, PA.0–PA.3) The ML63326 has Port 8, Port 9 and Port A input/output ports. 10.5.1 Port 8, Port 9, Port A Configuration The circuit configuration for ports 8, 9 and A is shown in Figure 10-6.

  • Page 145: Port 8, Port 9, Port A Registers

    *: The bits P83DIR and P82DIR have to be set to "1" or "0" before executing an external memory transfer instruction (MOVXB) or carrying out voice synthesis. The pins P8.3 and P8.2 are not present in the ML63326. For details, see Chapter 11, "External Memory Transfer Function" and Chapter 13, "Voice Synthesis."...
  • Page 146 *: Bits P83 and P82 have to be set to "1" or "0" before executing an external memory transfer instruction (MOVXB) or carrying out voice synthesis. The pins P8.3 and P8.2 are not present in the ML63326. For details, see Chapter 11, "External Memory Transfer Function" and Chapter 13, "Voice Synthesis."...
  • Page 147 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) At system reset the port data registers are set to "0". When data is written to a port data register, the actual pin change timing is at the rising edge of the system clock for state 2 of the write instruction.
  • Page 148 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (3) Port control registers (P8CON0, P9CON0, P9CON1, PACON0, PACON1) The port 8 control register 0 (P8CON0), the port 9 control registers 0/1 (P9CON0, P9CON1), and port A control registers 0/1 (PACON0, PACON1) are 4-bit special function registers (SFRs) used to select port input/output mode.
  • Page 149 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) • Port 9 bit 3 bit 2 bit 1 bit 0 P9CON0 (027H) P91MD1 P91MD0 P90MD1 P90MD0 (R/W) Port 9.1 input/output mode select Input mode Output mode bit 3 bit 2...
  • Page 150 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) • Port A bit 3 bit 2 bit 1 bit 0 PACON0 (02AH) PA1MD1 PA1MD0 PA0MD1 PA0MD0 (R/W) Port A.1 input/output mode select Input mode Output mode bit 3 bit 2...
  • Page 151 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (4) Port mode registers (P8MOD, P9AMOD) P8MOD and P9AMOD are 4-bit special function registers (SFRs) that enable the function of access by external memory transfer instruction (MOVXB) which is a secondary function of the respective ports.
  • Page 152 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (5) Voice synthesis when using an external memory When carrying out voice synthesis using an external memory, the RD signal is output at P8.0 and the data from the external memory is input via P9 (P9.3–P9.0) and PA (PA.3–PA.0).

  • Page 153: Port B (Pb.0-Pb.3)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.6 Port B (PB.0–PB.3) The ML63326 has Port B, a 4-bit input/output port. 10.6.1 Port B Configuration The circuit configuration for port B is shown in Figure 10-8. Data bus...

  • Page 154: Port B Registers

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.6.2 Port B Registers (1) Port B direction register (PBDIR) PBDIR is a 4-bit special function register (SFR) which specifies the port input/output direction for each bit. Pins corresponding to PBDIR bits set to "0" are input, and those corresponding to bits set to "1"...
  • Page 155 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (3) Port B control registers (PBCON0, PBCON1) The port B control registers 0/1 (PBCON0, PBCON1) are 4-bit special function registers (SFRs) used to select port input/output mode. The input mode can be pull-down resistor input, pull-up resistor input or high-impedance input.
  • Page 156 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (4) Port B mode register (PBMOD) PBMOD is a 4-bit special function register (SFR) used to select the sampling frequency when port B is used as an external interrupt. It is also used to select port B secondary functions other than external interrupt.
  • Page 157 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (5) Port B interrupt enable register (PBIE) PBIE is a 4-bit special function register (SFR) that enables/disables individual bits when port B is used as an external interrupt input. At system reset, PBIE is cleared to "0" and all bits of port B are initialized to the interrupt disabled state.

  • Page 158: Port B External Interrupt Function (External Interrupt 0)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.6.3 Port B External Interrupt Function (External Interrupt 0) Port B has external interrupt 0 allocated as secondary function. Individual bits of port B can be enabled/disabled. External interrupt generation for port B is triggered by the falling edge of the 128 Hz or 4 kHz time base counter, which is the sampling clock.

  • Page 159: Port E (Pe.0-Pe.3)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.7 Port E (PE.0–PE.3) The ML63326 has Port E, a 4-bit input/output port. 10.7.1 Port E Configuration The circuit configuration for port E is shown in Figure 10-12. Data bus...

  • Page 160: Port E Registers

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.7.2 Port E Registers (1) Port E direction register (PEDIR) PEDIR is a 4-bit special function register (SFR) which specifies the port input/output direction for each bit. Pins corresponding to PEDIR bits set to "0" are input, and those corresponding to bits set to "1"...
  • Page 161 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (3) Port E control registers (PECON0, PECON1) The port E control registers 0/1 (PECON0, PECON1) are 4-bit special function registers (SFRs) used to select port input/output mode. The input mode can be pull-down resistor input, pull-up resistor input or high-impedance input.
  • Page 162 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (4) Port E mode register (PEMOD) PEMOD is a 4-bit special function register (SFR) used to select the sampling frequency when PE.3 is used as an external interrupt. It is also used to select port E secondary functions other than external interrupt.

  • Page 163: Port E.3 External Interrupt Function (External Interrupt 2)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.7.3 Port E.3 External Interrupt Function (External Interrupt 2) Port E.3 has external interrupt 2 allocated as secondary function. External interrupt generation for PE.3 is triggered by the falling edge of the 128 Hz or 4 kHz time base counter, which is the sampling clock.

  • Page 164: Port F (Pf.0-Pf.3)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.8 Port F (PF.0–PF.3) The ML63326 has Port F, a 4-bit input/output port. 10.8.1 Port F Configuration The circuit configuration for port F is shown in Figure 10-16. Data bus...

  • Page 165: Port F Registers

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.8.2 Port F Registers (1) Port F direction register (PFDIR) PFDIR is a 4-bit special function register (SFR) which specifies the port input/output direction for each bit. Pins corresponding to PFDIR bits set to "0" are input, and those corresponding to bits set to "1"...
  • Page 166 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (3) Port F control registers (PFCON0, PFCON1) The port F control registers 0/1 (PFCON0, PFCON1) are 4-bit special function registers (SFRs) used to select port input/output mode. The input mode can be pull-down resistor input, pull-up resistor input or high-impedance input.
  • Page 167 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (4) Port F mode register (PFMOD) PFMOD is a 4-bit special function register (SFR) used to select the sampling frequency when port F is used as an external interrupt. The external interrupt sampling frequency can be selected as either 128 Hz or 4 kHz.
  • Page 168 ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) (5) Voice synthesis when using an external memory The pins PF.2, PF.1, and PF.0 output the high order 3-bit address (VA18–VA16) when carrying out voice synthesis using an external memory. These pins will be in the normal port state when carrying out voice synthesis using the ROM inside the chip.

  • Page 169: Port F External Interrupt Function (External Interrupt 3)

    ML63326 User's Manual Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.8.3 Port F External Interrupt Function (External Interrupt 3) Port F has external interrupt 3 allocated as secondary function. External interrupt generation for PF is triggered by the falling edge of the 128 Hz or 4 kHz time base counter, which is the sampling clock.

  • Page 170: Chapter 11 External Memory Transfer Function (Extmem)

    Chapter 11 External Memory Transfer Function (EXTMEM)

  • Page 172: Overview

    Chapter 11 External Memory Transfer Function (EXTMEM) 11.1 Overview In the ML63326, the character data in the voice ROM area inside the chip or the character data in the memory area external to the chip can be accessed using the external memory transfer instruction (MOVXB).

  • Page 173: Connection With The External Memory

    ML63326 User's Manual Chapter 11 External Memory Transfer Function (EXTMEM) 11.2 Connection with the External Memory The secondary port functions required when using the external memory transfer instruction are shown in Table 11-1, and Figure 11-1 shows the diagram of connections with the external memory.

  • Page 174: External Memory Address Space

    ML63326 User's Manual Chapter 11 External Memory Transfer Function (EXTMEM) Power supply for external memory P7, P6, P5, P4 (16-bit) A15–A0 IC power PA, P9 (8-bit) D7–D0 supply P8.0 P8.1 External memory ML63326 Figure 11-1 Connection to External Memory 11.3 External Memory Address Space A maximum of 16 address lines can be selected as port secondary functions, allowing access to 64 Kbytes of external memory.

  • Page 175: Setting Of Secondary Port Functions

    ML63326 User's Manual Chapter 11 External Memory Transfer Function (EXTMEM) 11.4 Setting of Secondary Port Functions The secondary functions of the port need to be set in order to execute the external memory transfer instruction. This setting is necessary for accessing both the voice ROM inside the chip and the memory area external to the chip.

  • Page 176: Reading From External Memory

    ML63326 User's Manual Chapter 11 External Memory Transfer Function (EXTMEM) 11.6 Reading from External Memory Use the following procedure for reading data from the external memory. (1) Set the secondary functions of the ports required for executing the external memory transfer instruction.

  • Page 177: Reading From The Voice Rom Inside The Chip

    11.7 Reading from the Voice ROM inside the Chip The ML63326 has a voice ROM area inside the chip, and it is possible to set character data in this area. Since a ROM area of 128 Kbytes is present (0H–1FFFFH), PF.0 is assigned as the MSB of the address.

  • Page 178: Writing To External Memory

    ML63326 User's Manual Chapter 11 External Memory Transfer Function (EXTMEM) 11.8 Writing to External Memory Use the following procedure for writing data to the external memory. (1) Set the secondary functions of the ports required for executing the external memory transfer instruction.
  • Page 179 ML63326 User's Manual Chapter 11 External Memory Transfer Function (EXTMEM) 11-8...

  • Page 180: Chapter 12 Melody Driver (Melody63K)

    Chapter 12 Melody Driver (MELODY63K)

  • Page 182: Overview

    Chapter 12 Melody Driver (MELODY63K) 12.1 Overview The ML63326 has a melody circuit and buzzer circuit in the microcontroller section. While automatically reading melody data in ROM (program memory) as specified by an MSA instruction, the melody circuit outputs a melody signal via the MD and MDB pins or DACOUT and AOUT pins.

  • Page 183: Melody Driver Registers

    ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) 12.3 Melody Driver Registers (1) Tempo Register (TEMPO) TEMPO is a 4-bit special function register (SFR) that sets the tempo of the melody driver. bit 3 bit 2 bit 1 bit 0...
  • Page 184 ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) bit 3: MSF This flag indicates the melody output status. When an MSA instruction starts the melody, MSF is set to "1". After output of the last melody data (END bit is "1"), MSF is cleared to "0".

  • Page 185: Melody Circuit Operation

    ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) bit 1, 0: MBM1, MBM0 These bits select the buzzer output mode. Output of two types of intermittent tones, a single tone or a continuous tone can be selected. At system reset, MBM1 and MBM0 are cleared to "0", selecting output of intermittent tone 1.

  • Page 186: Tempo Data

    ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) 12.4.1 Tempo Data Tempo data defines the basic tone length. Tempo data is set in the tempo register (TEMPO). The tempos (number of counts per minute) set by TEMPO are shown in Table 12-1.

  • Page 187: Melody Data

    ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) 12.4.2 Melody Data Melody data is 14-bit format data in the program ROM defining tone, tone length and end tone. The melody data format is indicated in Figure 12-3. bit 15 bit 14...
  • Page 188 ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) Table 12-2 Tone and Tone Code Correspondence (continued) Tone code Frequency Tone (Hz) N6–N0 1260 1338 1394 1490 1560 1680 1771 1872 1986 2114 2341 2521 2621 2979 (2) Tone length code The tone length code is set in melody data bits 13 through 8.
  • Page 189 ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) Table 12-3 Tone Length and Tone Length Code Correspondence Tone length code Tone length L5–L0 Tone lengths specified by the tone length code and the tempo data are expressed by the following: 1.953125 ¥...

  • Page 190: Melody Circuit Application Example

    ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) 12.4.3 Melody Circuit Application Example An example melody is shown in Figure 12-4. Table 12-4 lists the note codes for the melody shown in Figure 12-4. = 120 Figure 12-4 Example Melody...

  • Page 191: Buzzer Circuit Operation

    ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) 12.5 Buzzer Circuit Operation When EMBD (bit 2 of MDCON) is set to "1", a buzzer driver signal is sent to the melody driver output pins (MD, MDB) or DACOUT and AOUT pins.
  • Page 192 ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) EMBD 8 Hz Output MD (a) MBM1 = 0, MBM0 = 0 (intermittent tone 1) EMBD 8 Hz 1 Hz Output MD (b) MBM1 = 0, MBM0 = 1 (intermittent tone 2)

  • Page 193: Melody/Buzzer Output Selector Circuit

    ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) 12.6 Melody/Buzzer Output Selector Circuit The melody output and the buzzer output can be made respectively at pins MD and MDB or pins DACOUT and AOUT. It is possible to select which pins to output each of these waveforms using PD1 (bit 1 of PDD) and PD0 (bit 0 of PDD).

  • Page 194: Differences With Voice Synthesis Section Melody/Buzzer Output

    Chapter 12 Melody Driver (MELODY63K) 12.7 Differences with Voice Synthesis Section Melody/Buzzer Output While the ML63326 has melody drivers built into the microcontroller section and the voice synthesis section, the driving methods are different in these two sections. The differences in the melody outputs of the microcontroller section and the voice synthesis section are shown in Table 12-6 and the differences in the buzzer outputs are shown in Table 12-7.
  • Page 195 ML63326 User's Manual Chapter 12 Melody Driver (MELODY63K) 12-14...

  • Page 196: Chapter 13 Voice Synthesis

    Chapter 13 Voice Synthesis...

  • Page 198: Overview

    Chapter 13 Voice Synthesis 13.1 Overview The ML63326 has a built-in voice synthesis section. This voice synthesis section has the functions of melody output and buzzer output in addition to voice output. Each of these types of output data is stored in the internal 1-Mbit (128 Kbytes) mask ROM or in the externally connected memory of up to a maximum of 4 Mbits (512 Kbytes).
  • Page 199 Address during PF.2–PF.0 the MOVXB instruction P7.3–P7.0 P6.3–P6.0 P5.3–P5.0 P4.3–P4.0 PA.3–PA.0 P9.3–P9.0 Data bus Selector SPEN ENVOICE PCMOD0 To interrupt SP(+) circuit Voice synthesis core section AMP2 SP(–) PCIE To interrupt HSCLK Timing control section SPIN circuit ADPCM 1-Mbit DACOUT Melody/ buzzer AMP1...

  • Page 200: Registers Related To The Voice Synthesis Section

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.3 Registers Related to the Voice Synthesis Section (1) Phrase setting register 0 (P2D), phrase setting register 1 (P3D) P2D and P3D are 4-bit special function registers (SFRs) for setting the 8-bit phrase address.
  • Page 201 ML63326 User's Manual Chapter 13 Voice Synthesis (3) Voice synthesis control register 1 (PCDIR) PCDIR is a 4-bit special function register (SFR) for controlling the voice synthesis section. PCDIR is a write-only register and all read operations to this register are ignored.
  • Page 202 ML63326 User's Manual Chapter 13 Voice Synthesis (5) Port 8 data register (P8D) P8D is a 4-bit special function register (SFR) whose low-order 2 bits P80 and P81 set the output value (see Chapter 10, "Ports" for details). The high-order 2 bits P82 and P83 of this register are used for selecting voice synthesis or the external memory transfer instruction, and for selecting the internal voice ROM area or the external memory area.
  • Page 203 ML63326 User's Manual Chapter 13 Voice Synthesis (7) Voice/melody-buzzer output control register 0 (PDD) PDD is a 4-bit special function register (SFR) that is used for the control of the waveforms output at the DACOUT/AOUT pins and the MD/MDB pins, and is also used when a write operation is made to the external memory using the external memory transfer instruction.
  • Page 204 ML63326 User's Manual Chapter 13 Voice Synthesis (8) Voice/melody-buzzer output control register 1 (PDDIR) PDDIR is a 4-bit special function register (SFR) for controlling voice/melody-buzzer output. PDDIR is a write-only register and all read operations to this register are ignored.

  • Page 205: Voice Rom

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.4 Voice ROM 13.4.1 Voice ROM Configuration Figure 13-2 shows the configuration of the voice ROM. The voice ROM is composed of the phrase address management area, the test data area, and the user data area.

  • Page 206: Creation Of Voice Rom Store Data

    Voice data creation is completed. Note: The conversion to voice data using the voice analysis tool of step r is undertaken by Oki. The determination of the different parameters in steps q and w are to be made by the customers.

  • Page 207: Voice Synthesis Section Clock Input Frequency

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.5 Voice Synthesis Section Clock Input Frequency The clock used in the voice synthesis section is a high-speed clock supplied from the high- speed clock generator circuit and is basically intended to have frequency of 2.048 MHz.

  • Page 208: Operation Of The Voice Synthesis Section

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.6 Operation of the Voice Synthesis Section The voice synthesis section has the functions of voice, melody, and buzzer outputs. 13.6.1 Description of Pins Related to Voice Synthesis The DACOUT pin is the output pin of the 12-bit D/A converter, and the AOUT pin is the output pin of the amplifier whose input is the output of the 12-bit D/A converter.

  • Page 209: Phrase Address And Stop Code

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.6.2 Phrase Address and Stop Code The phrase address specifies which data is to be selected from among the data set in the phrase address management area of the memory area to be accessed.

  • Page 210: Voice

    13.7.1 Voice Reproduction Method The ML63326 allows the user to select from the three methods of 4-bit ADPCM, 8-bit straight PCM, and 8-bit non-linear PCM so as to meet various types of sounds and voice.

  • Page 211: Voice Output Procedure

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.7.3 Voice Output Procedure Follow the procedure given below when outputting voice. (Example using voice synthesis interrupt) q Select the output from DACOUT/AMPOUT. • Set PD1DIR and PD0DIR (bit 1 and bit 0 of PDDIR) to "1".
  • Page 212 ML63326 User's Manual Chapter 13 Voice Synthesis ! 3 3 Process the interrupt. • Set EVI (bit 3 of IE0) to "0". • Set PC2 (bit 2 of PCD) to "1". ! 4 For reproducing the second and subsequent phrases, first set EVI (bit 3 of IE0) to "1", and repeat steps o to ! 3 after enabling the voice synthesis interrupt.
  • Page 213 ML63326 User's Manual Chapter 13 Voice Synthesis PCDIR "7H" !3 !0 PC2 (CS) PC1 (ENVOICE) PC0 (Start) Phrase address data transfer Phrase address data transfer    P3D, P2D Phrase address setting of 1st sound Phrase address setting of 2nd sound...

  • Page 214: Voice Output Duration

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.8 Voice Output Duration Voice output duration can be obtained by the following expression: voice output duration = voice ROM capacity/bit rate = voice ROM capacity/(sampling frequency × bit length) Table 13-4 shows the maximum voice output duration for each sampling frequency and voice ROM capacity.

  • Page 215: Melody

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.9 Melody The melody circuit starts the melody output from the MD/MDB pins or the DACOUT/AOUT pins when the tempo and start address are stored in the phrase address management area and then the phrase in which the melody has been set is started from the interface circuit.
  • Page 216 ML63326 User's Manual Chapter 13 Voice Synthesis Table 13-5 Melody Tempos (continued) TEMPO Tempo = 83.3 = 78.1 = 73.5 = 69.4 = 65.8 = 62.5 = 59.5 = 56.8 = 54.3 = 52.1 = 50 = 48.1 = 46.3 = 44.6...

  • Page 217: Melody Data

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.9.2 Melody Data The melody data is the data in the memory that defines the tone, tone length, and the end tone, and consists of two bytes. The melody data format is shown in Figure 13-4.
  • Page 218 ML63326 User's Manual Chapter 13 Voice Synthesis Table 13-6 Tone and Tone Code Correspondence Tone code Frequency Tone (Hz) N7–N0 261.22 277.06 293.58 310.68 329.90 349.73 369.94 392.64 415.58 441.38 467.15 492.31 524.59 556.52 587.16 621.36 659.79 695.65 744.19 780.49 831.17...
  • Page 219 ML63326 User's Manual Chapter 13 Voice Synthesis (2) Tone length code The tone length code is set in the first byte of the melody data. Table 13-7 indicates the relation between tone length and tone length code (L5 to L0).
  • Page 220 ML63326 User's Manual Chapter 13 Voice Synthesis Table 13-8 Rest and Rest Code Correspondence Rest code Rest L5–L0 Tone lengths specified by the tone length code and the tempo data are expressed by the following: 1.5 ¥ (TP + 1) ¥ (L + 1) ms...

  • Page 221: Melody Circuit Application Example

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.9.3 Melody Circuit Application Example The example of outputting the notes shown in Figure 13-5 is given below. = 120 Figure 13-5 Example Melody Table 13-9 lists the note codes for the melody shown in Figure 13-5.

  • Page 222: Melody Output Procedure

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.9.4 Melody Output Procedure The procedure for outputting a melody is basically the same as the method of voice output described in Section 13.7.3. The distinction between voice and melody is made only by the data set in the phrase address management area and the user data area of the voice ROM.
  • Page 223 ML63326 User's Manual Chapter 13 Voice Synthesis PCDIR "7H" !3 !0 PC1 (ENVOICE) Phrase address data transfer Phrase address data transfer     P3D, P2D Phrase address setting of 1st melody Phrase address setting of 2nd melody High-speed...

  • Page 224: Buzzer

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.10 Buzzer The buzzer output is made at the MD/MDP pins or the DACOUT/AOUT pins when the phrase with the buzzer setting is started from the interface circuit. Buzzer output is available when the frequency and sound type have been set in the phrase address management area.

  • Page 225: Buzzer Output Procedure

    ML63326 User's Manual Chapter 13 Voice Synthesis 13.10.1 Buzzer Output Procedure Follow the procedure below when making a buzzer output. q Set which pin to use for the output among DACOUT/AOUT and MD/MDB. • Set PD1DIR and PD0DIR (bit 1 and bit 0 of PDDIR) to "1".

  • Page 226: Example Of Connections Made For Extending The Voice Data Area

    13.11 Example of Connections Made for Extending the Voice Data Area The ML63326 has an internal 128-Kbyte ROM as the voice synthesis data area. In addition, the voice synthesis data area can be extended up to a maximum of 640 Kbytes by connecting a 512-Kbyte ROM externally.

  • Page 227: Example Of Connections Made When Using A Piezoelectric Speaker

    13.12 Example of Connections Made When Using a Piezoelectric Speaker The ML63326 has two built-in amplifiers that can directly drive a piezoelectric speaker. When using this amplifier, it is possible to output the voice and other sounds from a piezoelectric speaker by externally connecting one capacitor and two resistors.

  • Page 228: Chapter 14 Shift Register (Sft)

    Chapter 14 Shift Register (SFT)

  • Page 230: Overview

    Chapter 14 Shift Register (SFT) Chapter 14 Shift Register (SFT) 14.1 Overview The ML63326 has one internal 8-bit shift register channel for clock synchronous communi- cation. The shift register is synchronized with the clock specified by the shift register control register 0 (SFTCON0), and can perform 8-bit data send and receive simultaneously.

  • Page 231: Shift Registers

    ML63326 User's Manual Chapter 14 Shift Register (SFT) 14.3 Shift Registers (1) Shift register L/H (SFTRL, SFTRH) SFTRL and SFTRH are 4-bit special function registers (SFRs) used to write shift register send data and to read receive data. bit 3...
  • Page 232 ML63326 User's Manual Chapter 14 Shift Register (SFT) (2) Shift register control registers (SFTCON0, SFTCON1) SFTCON0 and SFTCON1 are 4-bit special function registers (SFRs) that control shift register operation. At system reset both are initialized to "0". bit 3 bit 2...

  • Page 233: Shift Register Operation

    ML63326 User's Manual Chapter 14 Shift Register (SFT) 14.4 Shift Register Operation The shift register can be set to master or slave mode, and to MSB first or LSB first. The send data is written to the shift register (SFTRL, SFTRH), and transfer is started by setting bit 0 (ENTR) of the shift control register 1 (SFTCON1) to "1".
  • Page 234 ML63326 User's Manual Chapter 14 Shift Register (SFT) SFTCON1 Write signal ENTR SCLK (PE.2) SOUT (PE.1) (PE.0) System clock SFTINT Figure 14-2 Shift Register Operation Timing Note : Setting the ENTR bit to "1" in the slave mode should be done when the PE.2/SCLK pin is high.

  • Page 235: Shift Register Application Example

    ML63326 User's Manual Chapter 14 Shift Register (SFT) 14.5 Shift Register Application Example An example of register setting for clock synchronous communication using shift register is described below. (1) Set the supported port modes (secondary function). Port control Master mode register Bit 2 = "1"...

  • Page 236: Chapter 15 Lcd Driver (Lcd)

    Chapter 15 LCD Driver (LCD)

  • Page 238: Overview

    Chapter 15 LCD Driver (LCD) 15.1 Overview The ML63326 has an internal dot matrix LCD driver. The ML63326 has 64 segment outputs and can drive up to 1024 (64 seg. ¥ 16 com.) dots. The LCD driver can be software-selected to all OFF, all ON or power down mode, 1/4 or 1/5 bias, selectable duty from 1/1 to 1/16, and adjustable (16-tone) contrast.

  • Page 239: Lcd Driver Registers

    ML63326 User's Manual Chapter 15 LCD Driver (LCD) 15.3 LCD Driver Registers (1) Display control register (DSPCON0) DSPCON0 is a 4-bit special function register (SFR) controlling LCD driver operation. bit 3 bit 2 bit 1 bit 0 DSPCON0 (090H) BISEL...
  • Page 240 ML63326 User's Manual Chapter 15 LCD Driver (LCD) (2) Display control register (DSPCON1) DSPCON1 is a 4-bit special function register (SFR) used to select the LCD driver duty. At system reset, bits of DSPCON1 are initialized to "0". bit 3...
  • Page 241 ML63326 User's Manual Chapter 15 LCD Driver (LCD) (4) Display registers (DSPR0 to DSPR255) DSPR0 to DSPR255 are segment output data registers for the dot matrix LCD driver allocated to RAM BANK 1. The correspondence between display registers and segment outputs is shown below.

  • Page 242: Lcd Driver Operation

    ML63326 User's Manual Chapter 15 LCD Driver (LCD) 15.4 LCD Driver Operation The display duty is selected from 1/1 to 1/16 using DSPCON. The frame frequency for each duty ratio is indicated in Table 15-1. Depending on the duty selected, the common signal (COM1 to COM16) is generated, and data written in synchronization with that common signal to the display registers (DSPR0 to DSPR255) is output to the segment driver.

  • Page 243: Bias Generator (Bias)

    ML63326 User's Manual Chapter 15 LCD Driver (LCD) 15.5 Bias Generator (BIAS) The bias generator is used to multiply and divide the voltage (V ) generated in the constant voltage circuit with an external capacitor connected to pins C1, C2 to generate V to V bias voltages for the LCD driver.
  • Page 244 ML63326 User's Manual Chapter 15 LCD Driver (LCD) To high-speed clock generator circuit Voltage doubler circuit Display contrast adjustment Constant voltage (CN3–0) circuit 1/4 bias select (BISEL = "1") Power down mode select BIAS (PDWN = "1") generator To LCD driver...
  • Page 245 ML63326 User's Manual Chapter 15 LCD Driver (LCD) Table 15-2 Display Contrast Adjusting Voltages (V (Ta = 25°C, V = 0 V) DSPCNT Voltage (V) Contrast CN3–0 Min. Typ. Max. 1.70 1.80 1.90 Light 1.74 1.84 1.94 1.78 1.88 1.98 1.82...

  • Page 246: Lcd Driver Output Waveform

    ML63326 User's Manual Chapter 15 LCD Driver (LCD) 15.6 LCD Driver Output Waveform Figures 15-4 (a) and 15-4 (b) show the output waveforms for 1/16 duty and 1/5 bias, and Figures 15-5 (a) and 15-5 (b) show the output waveforms for 1/8 duty and 1/4 bias.
  • Page 247 ML63326 User's Manual Chapter 15 LCD Driver (LCD) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 Frame frequency 64 Hz 8 9 10 11 12 13 14 15 16 1 2 9 10 11 12 13 14 15 16...
  • Page 248 ML63326 User's Manual Chapter 15 LCD Driver (LCD) Frame frequency 128 Hz 4 5 6 COM1 DD2,3 COM2 DD2,3 COM3 DD2,3 • • • • • • COM8 DD2,3 COM9–16 DD2,3 Figure 15-5 (a) 1/8 Duty, 1/4 Bias Common Output Waveform...
  • Page 249 ML63326 User's Manual Chapter 15 LCD Driver (LCD) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 Frame frequency 128 Hz 4 5 6 SEG0 DD2,3 SEG1 DD2,3 SEG2 DD2,3 Figure 15-5 (b) 1/8 Duty, 1/4 Bias Segment Output Waveform 15-12...

  • Page 250: Chapter 16 Battery Low Detect Circuit (Bld)

    Chapter 16 Battery Low Detect Circuit (BLD)

  • Page 252: Overview

    Chapter 16 Battery Low Detect Circuit (BLD) Chapter 16 Battery Low Detect Circuit (BLD) 16.1 Overview The ML63326 contains a battery low detect circuit (BLD). The battery low detect circuit detects when the battery voltage (supply voltage V ) falls below the judgment voltage value.

  • Page 253: Judgment Voltage

    ML63326 User's Manual Chapter 16 Battery Low Detect Circuit (BLD) 16.3 Judgment Voltage The value of the judgment voltage is selected by the software by setting the LD1 (bit 1 of BLDCON) and LD0 (bit 0 of BLDCON) bits. Table 16-1 lists judgment voltage and precision values.

  • Page 254: Battery Low Detect Circuit Operation

    ML63326 User's Manual Chapter 16 Battery Low Detect Circuit (BLD) 16.5 Battery Low Detect Circuit Operation The battery low detect circuit is turned ON or OFF by ENBL (bit 2 of BLDCON), and outputs to BLDF (bit 3 of BLDCON) the result of a comparison with the judgment voltage.
  • Page 255 ML63326 User's Manual Chapter 16 Battery Low Detect Circuit (BLD) 16-4...

  • Page 256: Chapter 17 Power Supply Circuit (Power)

    Chapter 17 Power Supply Circuit (POWER)

  • Page 258: Overview

    Chapter 17 Power Supply Circuit (POWER) Chapter 17 Power Supply Circuit (POWER) 17.1 Overview The ML63326 contains a constant voltage circuit for the internal logic power supply (V a constant voltage circuit for the LCD bias reference power supply (V ), and a voltage doubler circuit for the power supply for high-speed oscillation (V 17.2 Power Supply Circuit Configuration...

  • Page 259: Power Supply Circuit Operation

    ML63326 User's Manual Chapter 17 Power Supply Circuit (POWER) 17.3 Power Supply Circuit Operation The V output of the power supply for the internal logic circuits is automatically switched to the V level when the time base counter is reset, and changes to 1.7 V immediately after the reset state is released.

  • Page 260: Appendixes

    Appendixes...

  • Page 262: Appendix A List Of Special Function Registers

    ML63326 User's Manual Appendix A Appendix A List of Special Function Registers The Special Function Registers of the ML63326 are listed in Table A. Table A Special Function Register List Initial value Register name Symbol Address bit 3 bit 2...
  • Page 263 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value at system Register name Symbol Address bit 3 bit 2 bit 1 bit 0 reset Port 7 control register 0 P7CON0 020H P71MD1 P71MD0 P70MD1 P70MD0...
  • Page 264 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address bit 3 bit 2 bit 1 bit 0 at system reset Port E mode register PEMOD 040H PE2MOD PE1MOD PE0MOD Port F control register 0...
  • Page 265 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address bit 3 bit 2 bit 1 bit 0 at system reset Timer 0 control register 0 TM0CON0 070H — FMEAS0 TM0ECAP TM0RUN...
  • Page 266 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address bit 3 bit 2 bit 1 bit 0 at system reset Shift register L SFTRL 0A0H Shift register H SFTRH 0A1H Shift register control register 0...
  • Page 267 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value at system Register name Symbol Address Segment bit 3 bit 2 bit 1 bit 0 reset Display register 0 DSPR0 100H COM4 COM3 COM2 COM1 R/W Undefined...
  • Page 268 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value at system Register name Symbol Address Segment bit 3 bit 2 bit 1 bit 0 reset Display register 36 DSPR36 124H COM4 COM3 COM2 COM1 R/W Undefined...
  • Page 269 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value at system Register name Symbol Address Segment bit 3 bit 2 bit 1 bit 0 reset Display register 72 DSPR72 148H COM4 COM3 COM2 COM1 R/W Undefined...
  • Page 270 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address Segment bit 3 bit 2 bit 1 bit 0 at system reset Display register 108 DSPR108 16CH COM4 COM3 COM2 COM1 R/W Undefined...
  • Page 271 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address Segment bit 3 bit 2 bit 1 bit 0 at system reset Display register 144 DSPR144 190H COM4 COM3 COM2 COM1 R/W Undefined...
  • Page 272 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value Segment at system Register name Symbol Address bit 3 bit 2 bit 1 bit 0 reset Display register 180 DSPR180 1B4H COM4 COM3 COM2 COM1 R/W Undefined...
  • Page 273 ML63326 User's Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address Segment bit 3 bit 2 bit 1 bit 0 at system reset Display register 216 DSPR216 1D8H COM4 COM3 COM2 COM1 R/W Undefined...

  • Page 274: Appendix B Package Dimensions

    The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature, and times).

  • Page 275: Appendix C Input/Output Circuit Configuration

    ML63326 User's Manual Appendix C Appendix C Input/Output Circuit Configuration (1) I/O Port (P8.0, P8.1, P9.0–P9.3, PA.0–PA.3, PB.0–PB.3, PE.0–PE.3, PF.0–PF.3) Pull-up/pull-down control Gate control circuit Output data Output control Input data Schmitt trigger input (2) Input Port (P0.0–P0.3) Pull-up/pull-down control...
  • Page 276 ML63326 User's Manual Appendix C (3) Low-Speed Clock Generator Time base clock CMOS input (TBCCLK) Inside the IC (4) High-Speed Clock Generator Oscillation start CMOS input OSC0 High-speed clock (HSCLK) OSC1 Inside the IC (5) RESET, TST1, TST2, VTEST, and SPEN Inputs...

  • Page 277: Appendix D Peripheral Circuit Examples

    ML63326 User's Manual Appendix D Appendix D Peripheral Circuit Examples 32.768 kHz crystal COM1–16 SEG0–63 5.0 V PF.3 PF.2 PF.1 5 to 25 pF PF.0 P7.3 1.0 mF P7.2 P7.1 2.0 to 5.5 V P7.0 P6.3 P6.2 0.1 mF P6.1 P6.0...
  • Page 278 ML63326 User's Manual Appendix D COM1–16 SEG0–63 5.0 V PF.3 1.5 MW PF.2 (approx. 32 kHz) PF.1 PF.0 P7.3 1.0 mF P7.2 P7.1 2.0 to 5.5 V P7.0 P6.3 P6.2 0.1 mF P6.1 P6.0 P5.3 P5.2 External P5.1 P5.0 memory 1.0 mF...
  • Page 279 ML63326 User's Manual Appendix D 32.768 kHz crystal COM1–16 SEG0–63 5.0 V PF.3 PF.2 PF.1 5 to 25 pF PF.0 P7.3 1.0 mF P7.2 P7.1 2.0 to 5.5 V P7.0 P6.3 P6.2 0.1 mF P6.1 P6.0 P5.3 P5.2 External P5.1 P5.0...
  • Page 280 ML63326 User's Manual Appendix D 32.768 kHz crystal COM1–16 SEG0–63 5.0 V PF.3 PF.2 PF.1 5 to 25 pF PF.0 P7.3 1.0 mF P7.2 P7.1 2.0 to 5.5 V P7.0 P6.3 P6.2 0.1 mF P6.1 P6.0 P5.3 P5.2 External P5.1 P5.0...
  • Page 281 ML63326 User's Manual Appendix D 32.768 kHz crystal COM1–16 SEG0–63 PF.3 PF.2 PF.1 5 to 25 pF PF.0 P7.3 1.0 mF P7.2 P7.1 2.0 to 5.5 V P7.0 P6.3 P6.2 0.1 mF P6.1 P6.0 P5.3 P5.2 P5.1 P5.0 1.0 mF P4.3...

  • Page 282: Appendix E Electrical Characteristics

    ML63326 User's Manual Appendix E Appendix E Electrical Characteristics (Preliminary) Absolute Maximum Ratings = 0 V) Parameter Symbol Condition Rating Unit Power Supply Voltage 1 Ta = 25°C –0.3 to +1.6 Power Supply Voltage 2 Ta = 25°C –0.3 to +2.9 Power Supply Voltage 3 Ta = 25°C...
  • Page 283 ML63326 User's Manual Appendix E Recommended Operating Conditions = 0 V) Parameter Symbol Condition Range Unit Operating Temperature — –20 to +70 °C — 2.0 to 5.5 2.0 to 5.5 — Operating Voltage 2.0 to 5.5 — 0.5 to (AV –...
  • Page 284 ML63326 User's Manual Appendix E • Typical characteristics of low-speed RC oscillation When V = 1.8 V Reference data 1000 1000 10000 [kW] • Typical characteristics of high-speed RC oscillation When V = 3.6 V Reference data 10000 1000 1000...
  • Page 285 ML63326 User's Manual Appendix E DC Characteristics = AV = 2.0 to 5.5 V, V = AV = 0 V, Ta = –20 to +70°C unless otherwise specified) Mea- Parameter Symbol Condition Min. Typ. Max. Unit suring Circuit 1/5 bias, 1/4 bias Voltage (Ta = 25°C)
  • Page 286 ML63326 User's Manual Appendix E DC Characteristics (continued) = AV = 2.0 to 5.5 V, V = AV = 0 V, Ta = –20 to +70°C unless otherwise specified) Mea- Parameter Symbol Condition Min. Typ. Max. Unit suring Circuit = 2.0 V —...
  • Page 287 ML63326 User's Manual Appendix E DC Characteristics (continued) = AV = 3.0 V, V = AV = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified) Mea- Parameter Symbol Condition Min. Typ. Max. Unit suring Circuit CPU is in HALT state.
  • Page 288 ML63326 User's Manual Appendix E DC Characteristics (continued) = AV = 3.0 V, V = 1.1 V, V = 2.2 V, V = 3.3 V, V = 4.4 V, = 5.5 V, V = AV = 0 V, Ta = –20 to +70°C unless otherwise specified)
  • Page 289 ML63326 User's Manual Appendix E DC Characteristics (continued) = AV = 3.0 V, V = 1.1 V, V = 2.2 V, V = 3.3 V, V = 4.4 V, = 5.5 V, V = AV = 0 V, Ta = –20 to +70°C unless otherwise specified)
  • Page 290 ML63326 User's Manual Appendix E DC Characteristics (continued) = AV = 3.0 V, V = 1.1 V, V = 2.2 V, V = 3.3 V, V = 4.4 V, = 5.5 V, V = AV = 0 V, Ta = –20 to +70°C unless otherwise specified)
  • Page 291 ML63326 User's Manual Appendix E Measuring circuit 1 OSC0 OSC1 : 0.1 mF *1 RC Oscillator *2 RC Oscillator : 1 mF : 15 pF : 30 pF : 30 pF Crystal unit : AT-49 4.096 MHz Crystal Oscillator Crystal Oscillator (Daishinku Corp.-make)
  • Page 292 ML63326 User's Manual Appendix E Measuring circuit 3 INPUT OUTPUT Measuring circuit 4 Waveform Monitoring INPUT OUTPUT *5 Measured at the specified input pins. Appendix-31...
  • Page 293 ML63326 User's Manual Appendix E AC Characteristics (Serial Interface, Shift Register) (Target value) = AV = 2.0 to 5.5 V, V = AV = 0 V, V = 5.0 V, Ta = –20 to +70°C unless otherwise specified) Min. Typ.
  • Page 294 ML63326 User's Manual Appendix E AC Characteristics (External Memory Interface) (Target value) = AV = 2.0 to 5.5 V, V = 0 V, V = 5.0 V, Ta = –20 to +70°C unless otherwise specified) (1) Reading from External Memory (a) When CPU operates at 32.768 kHz...
  • Page 295 ML63326 User's Manual Appendix E (2) Writing to External Memory (a) When CPU operates at 32.768 kHz Min. Typ. Max. Parameter Symbol Condition Unit Write Cycle Time — — — Address Setup Time — — 30.5 — Write Time —...

  • Page 296: Appendix F Instruction List

    ML63326 User's Manual Appendix F Appendix F Instruction List The format used in the list of instructions is indicated below. INSTRUCTION CODE FLAG MNEMONIC OPERATION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G Flags marked with (÷) are...
  • Page 297 ML63326 User's Manual Appendix F Transfer Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G MOV direct,A direct¨A 1 0 0 r — — —...
  • Page 298 ML63326 User's Manual Appendix F Rotate Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ ÷ — ROL sfr C¨{ }¨C,A¨sfr 0 1 0 0 0 1 0 r ÷...
  • Page 299 ML63326 User's Manual Appendix F Increment/Decrement Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ ÷ — INC sfr sfr,A¨sfr+1 0 1 0 0 0 0 0 r ÷...
  • Page 300 ML63326 User's Manual Appendix F Arithmetic Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ ÷ — ADD sfr,A sfr,A¨sfr+A 0 1 0 0 1 0 0 r ÷...
  • Page 301 ML63326 User's Manual Appendix F Arithmetic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G sfr,A¨decimal adjustment ÷ ÷ — ADCD sfr,A 0 1 0 0 1 1 0 r {sfr+A+C} cur,A¨decimal adjustment...
  • Page 302 ML63326 User's Manual Appendix F Arithmetic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ ÷ — SUB sfr,A sfr,A¨sfr–A 0 1 0 0 1 1 1 r ÷...
  • Page 303 ML63326 User's Manual Appendix F Arithmetic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G sfr,A¨decimal adjustment ÷ ÷ — SBCD sfr,A 0 1 0 1 0 0 1 r {sfr–A–C}...
  • Page 304 ML63326 User's Manual Appendix F Compare Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ ÷ — CMP sfr,A sfr–A 0 1 0 1 0 1 0 r ÷...
  • Page 305 ML63326 User's Manual Appendix F Logic Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ — — AND sfr,A sfr,A¨sfr A 0 1 0 1 0 1 1 r ÷...
  • Page 306 ML63326 User's Manual Appendix F Logic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ — — OR ¥cur,#i4 cur,A¨cur i4 1 1 0 i OR [HL],#i4 [HL],A¨[HL] i4...
  • Page 307 ML63326 User's Manual Appendix F Mask Operation Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G Testing of all bits in sfr ÷ — —...
  • Page 308 ML63326 User's Manual Appendix F Mask Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G Clearing of all bits in cur ÷ — —...
  • Page 309 ML63326 User's Manual Appendix F Mask Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G Setting of all bits in cur MSET ¥cur,#m not masked by #m, ÷...
  • Page 310 ML63326 User's Manual Appendix F Mask Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G Inverting of all bits in ÷ — —...
  • Page 311 ML63326 User's Manual Appendix F Bit Operation Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ — — BTST ¥cur.n Bit testing of cur.n 0 1 1 n BTST [HL].n...
  • Page 312 ML63326 User's Manual Appendix F Bit Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G ÷ — — BNOT ¥cur.n cur.n¨cur.n,A¨cur 1 1 1 n ÷...
  • Page 313 ML63326 User's Manual Appendix F ROM Table Reference Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G MOVHB [HL], [HL],[HL+1]¨(RA) 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 — — —...
  • Page 314 ML63326 User's Manual Appendix F ROM Table Reference Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G MOVLB [HL], [HL],[HL+1]¨(RA) 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 — — —...
  • Page 315 ML63326 User's Manual Appendix F External Memory Transfer Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G MOVXB [HL], [HL],[HL+1]¨(RA) 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 — — —...
  • Page 316 ML63326 User's Manual Appendix F External Memory Transfer Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 MOVXB [HL], [HL],[HL+1]¨...
  • Page 317 ML63326 User's Manual Appendix F Stack Operation Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G (RSP)¨{FLAG,A,HL}, 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 — — —...
  • Page 318 ML63326 User's Manual Appendix F Conditional Branch Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G BC radr8 if C=1 then 0 0 0 0 1 0 1 a —...
  • Page 319 ML63326 User's Manual Appendix F Control Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G NO OPERATION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 —...

  • Page 320: Appendix G Mask Option

    Appendix G Appendix G Mask Option The ML63326 can select the crystal oscillation circuit or the RC oscillation circuit as the oscillation circuit of the low-speed clock generator circuit by mask option. To use the mask option, assign mask option data in the application program in accordance with the format below.
  • Page 321 ML63326 User's Manual Appendix G Appendix-60...
  • Page 322 ML63326 User's Manual First Edition: June 1999 Second Edition: September 1999 © © © © © 1999 Oki Electric Industry Co., Ltd. PEUL63326-02...

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