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ML63611 User's Manual
Chapter 3 CPU Control Functions
3.2
System Reset Mode (RST)
3.2.1 Transfer to and State of System Reset Mode
The ML63611 transfers to the system reset mode due to the following three causes:
(1) When the RESET pin is taken to the "H" level
When recognizing the reset signal, the signal input to the RESET signal is being sampled at 2 kHz.
Therefore, the width of the "H" level pulse applied to the RESET pin should be 1 ms or more.
(2) Detection of stoppage of the low frequency clock oscillations (mask option selection)
(3) Simultaneous key depression at the input port 0 (P0.0 to P0.3)
The system reset mode will be entered when there is a simultaneous key depression of a maximum of 4 bits
(pins) of Port 0. However, since this sampling is being made at 1 Hz, continue to press for more than about 2
to 3 seconds.
The number of bits pressed simultaneously can be selected by mask option to be 2 bits (P0.0, P0.1), 3 bits
(P0.0, P0.1, and P0.2), or 4 bits (P0.0, P0.1, P0.2, and P0.3). For details of the mask option settings, refer to
Section 1.3, "Mask Options" and the "MOGTOOL Mask Option Generator User's Manual".
The following operations are performed in the system reset mode.
(1) CPU is initialized.
(2) Bias reference voltage supply (V/R1, V/R2, V/R3) is energized.
(3) All LCD driver outputs are turned OFF and the outputs change to the V
(4) All special function registers (SFRs) are initialized. However, data RAM and the segment register for LCD
are not initialized.
After system reset processing, instruction execution begins from address 0000H.
Figure 3-2 shows the system reset generator circuit and Figure 3-3 shows the signals when a system reset is
generated.
RESET
V
SS
XT0
Low-speed
clock generator
XT1
circuit
P0.3
Input port 0
P0.2
simultaneous
key depression
P0.1
detection circuit
P0.0
Inside the IC
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
Low-speed clock
oscillations stoppage
detector circuit
Sampling
P0RST
Figure 3-2 System Reset Generator Circuit
3 – 2
level.
SS
2 kHz
Sampling
circuit
Mask option
1 Hz
4 Hz
circuit
OPTION B (D): 1.5 V (3.0 V), With regulator
RESET0
(Time base
counter reset)
S
Q
RESETS
(System reset)
R
circuit for LCD bias
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