Port A Registers - Oki ML63611 User Manual

ML63611 User's Manual
Chapter 10 Ports (INPUT, I/O PORT)

10.4.2 Port A Registers

(1) Port A data register (PAD)
PAD is a 4-bit special function register (SFR) used to set the output values for the port.
When a bit in the port direction register (PADIR) is set to "1" to select the output mode, the content of the
corresponding bit in the port data register (PAD) is output to the port (port A).
When a bit in the port data register (PAD) is read with the corresponding port direction register bit set to
output, the value of the bit in the port data register is read.
When a bit in the port data register (PAD) is read with the corresponding port direction register bit set to "0"
(input mode), the level of the corresponding pin is read.
• Port A
PAD (00AH)
Port A input/output data
At system reset all bits in the port A data register are set to "0". When data is written to the port A data
register, the actual pin change timing is at the rising edge of the system clock for state 2 of the write
instruction.
Figure 10-5 shows port A change timing.
CLK
Port A
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
bit 3
PA3
(R/W)
Write instruction
S1
Old data
Figure 10-5 Port A Change Timing
bit 2 bit 1
PA2 PA1
S2
10 – 8
OPTION B (D): 1.5 V (3.0 V), With regulator
bit 0
PA0
New data
circuit for LCD bias