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Oki ML63611 User Manual

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PEUL63611-02
ML63611
User's Manual
CMOS 4-bit microcontroller
Preliminary
SECOND EDITION
ISSUE DATE: Jun. 2001

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Summary of Contents for Oki ML63611

  • Page 1 PEUL63611-02 ML63611 User’s Manual CMOS 4-bit microcontroller Preliminary SECOND EDITION ISSUE DATE: Jun. 2001...
  • Page 2 Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range.
  • Page 3 Preface This manual describes the hardware of Oki’s original CMOS 4-bit microcontroller ML63611. Refer to the “nX-4/250, 300 Core Instruction Manual” for details of the 4-bit CPU core nX-4/250 which is built in the ML63611. The manuals related to the ML63611 is shown below.
  • Page 4 Notation Classification Notation Description Numeric value xxh, xxH Represents a hexadecimal number. Represents a binary number. Unit word, W 1 word = 16 bits byte, B 1 byte = 2 nibbles = 8 bits nibble, N 1 nibble = 4 bits mega-, M kilo-, K = 1024...

  • Page 5: Table Of Contents

    Overview..............................1-1 Features...............................1-1 Mask Options..............................1-5 Function List ...............................1-7 Block Diagram............................1-8 Pin Configuration............................1-12 1.6.1 ML63611 Pin Configuration .......................1-12 Pin Descriptions............................1-15 1.7.1 Descriptions of the Basic Functions of Each Pin ................1-15 1.7.2 Descriptions of the Secondary Functions of Each Pin.................1-19 1.7.3 Handling of Unused Pins........................1-20 Basic Timing.............................1-21...
  • Page 6 ML63611 User’s Manual Contents Chapter 4. Interrupt (INT) Overview..............................4-1 Interrupt Registers............................4-3 Interrupt Sequence ............................4-11 4.3.1 Interrupt Processing..........................4-11 4.3.2 Return from an Interrupt Routine ......................4-12 4.3.3 Interrupt Hold Instructions ........................4-12 Chapter 5. Clock Generator Circuit (OSC) Overview..............................5-1 Clock Generator Circuit Configuration.......................5-1 Low-Speed Clock Generator Circuit......................5-2...
  • Page 7 ML63611 User’s Manual Contents Chapter 10. Ports (INPUT, I/O PORT) 10-1 10.1 Overview..............................10-1 10.2 Ports List..............................10-1 10.3 Port 0 (P0.0–P0.3).............................10-2 10.3.1 Port 0 Configuration..........................10-2 10.3.2 Port 0 Registers ...........................10-2 10.3.3 Port 0 External Interrupt Function (External Interrupt 5)..............10-5 10.4 Port A (PA.0–PA.3) ..........................10-7 10.4.1 Port A Configuration...........................10-7...
  • Page 8 ML63611 User’s Manual Contents Chapter 14. Battery Low Detect Circuit (BLD) 14-1 14.1 Overview..............................14-1 14.2 Battery Low Detect Circuit Configuration....................14-1 14.3 Judgment Voltage .............................14-2 14.4 Battery Low Detect Circuit Register......................14-2 14.5 Battery Low Detect Circuit Operation ......................14-3 Chapter 15. Power Supply Circuit (POWER) 15-1 15.1 Overview..............................15-1...

  • Page 9: Chapter 1. Overview

    Chapter 1 Overview...

  • Page 10: Overview

    The ML63611 is a CMOS 4-bit microcontroller using Oki’s original CPU core nX-4/250. The ML63611 is provided with the mask options of eight items of selection including (1.5 V or 3.0 V) power supply specifications and (With or Without) the regulator circuit for the LCD bias reference voltage.
  • Page 11 ML63611 User’s Manual Chapter 1 Overview c. Processing speed • 2 clocks per machine cycle, with most instructions executed in 1 machine cycle • Minimum instruction execution time: 61 µs (@ 32.768 kHz system clock) 10 µs (@ 200 kHz system clock) 2.86 µs (@ 700 kHz system clock)
  • Page 12 ML63611 User’s Manual Chapter 1 Overview j. LCD driver Segment-type LCD drivers built-in The following pin modes can be specified for L0 to L63 by the mask option generator setting. (Refer to the “MOGTOOL Mask Option Generator User’s Manual”.) “ ” in the table below indicates that that particular function can be selected.
  • Page 13 ML63611 User’s Manual Chapter 1 Overview n. Timers, counters • 8-bit timer: 4 channels Selectable as auto-reload mode, capture mode, clock frequency measurement mode • Watchdog timer: 1 channel • 100 Hz timer: 1 channel 1/100 sec. measurement possible •...

  • Page 14: Mask Options

    Chapter 1 Overview Mask Options There are eight items in the mask option of the ML63611. Make the settings for the following items using the MOGTOOL mask option generator. Refer to the “MOGTOOL Mask Option Generator User’s Manual” for details of the method of making the settings.
  • Page 15 ML63611 User’s Manual Chapter 1 Overview SEG/COM/PORT/DATA selection of the LCD driver pins It is possible to make the pins L0 to L3 and L36 to L39 either SEG pins or COM pins. However, it is a maximum of four pins that can be selected as COM pins.

  • Page 16: Function List

    ML63611 User’s Manual Chapter 1 Overview Function List Table 1-1 lists the functions of the ML63611. The solid black circles within the chart indicate that the product has the particular function. Table 1-1 Function List Reference Function Symbol OPTION A...

  • Page 17: Block Diagram

    ML63611 User’s Manual Chapter 1 Overview Block Diagram Block diagrams of the ML63611 are shown in Figures 1-1, 1-2, 1-3 and 1-4. Asterisks (*) indicate port secondary functions. CPU CORE : nX-4/250 TIMING CON- (8 KW) TROL CON- TROL INSTRUCTION...
  • Page 18 ML63611 User’s Manual Chapter 1 Overview Asterisks (*) indicate port secondary functions. CPU CORE : nX-4/250 TIMING CON- (8 KW) TROL CON- TROL INSTRUCTION STACK DECODER CAL.S:16 levels REG.S:16 levels TM0CAP/TM1CAP* TIMER TM0OVF/TM1OVF* (1 KN) (8-bit, 4ch) T02CK* T13CK* RXC*...
  • Page 19 ML63611 User’s Manual Chapter 1 Overview Asterisks (*) indicate port secondary functions. CPU CORE : nX-4/250 TIMING CON- (8 KW) TROL CON- TROL INSTRUCTION STACK DECODER CAL.S:16 levels REG.S:16 levels TM0CAP/TM1CAP* TIMER TM0OVF/TM1OVF* (1 KN) (8-bit, 4ch) T02CK* T13CK* RXC*...
  • Page 20 ML63611 User’s Manual Chapter 1 Overview Asterisks (*) indicate port secondary functions. CPU CORE : nX-4/250 TIMING CON- (8 KW) TROL CON- TROL INSTRUCTION STACK DECODER CAL.S:16 levels REG.S:16 levels TM0CAP/TM1CAP* TIMER TM0OVF/TM1OVF* (1 KN) (8-bit, 4ch) T02CK* T13CK* RXC*...

  • Page 21: Pin Configuration

    ML63611 User’s Manual Chapter 1 Overview Pin Configuration 1.6.1 ML63611 Pin Configuration The ML63611 chip pin configuration and pad coordinates are shown in Figures 1-5 and Table 1-2 respectively. TRIMB5 TRIMB4 PE.3 TRIMB3 PE.2 TRIMDB1 PE.1 TRIMB2 PE.0 TRIMB1 PC.3 TRIMB0 PC.2...
  • Page 22 ML63611 User’s Manual Chapter 1 Overview Table 1-2 ML63611 Pad Coordinates Chip center: X = 0, Y = 0 Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) TST1 TST2 P0.0 P0.1 P0.2 P0.3...
  • Page 23 ML63611 User’s Manual Chapter 1 Overview Table 1-2 ML63611 Pad Coordinates (continued) Chip center: X = 0, Y = 0 Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) TRIMB5 TRIMB4 TRIMB3 TRIMDB1...

  • Page 24: Pin Descriptions

    1.7.1 Descriptions of the Basic Functions of Each Pin The basic functions of each pin of the ML63611 are listed in Table 1-3. Use of a slash (“/”) in a pin name indicates that the pin has a secondary function. See Table 1-4 for the secondary functions.
  • Page 25 ML63611 User’s Manual Chapter 1 Overview Table 1-3 Pin Description (Basic Functions) (continued) Classification Pad No. Function name Reset input pin: 2 kHz sampling circuit is equipped. Holding this pin to “H” level for 1 ms or more puts this...
  • Page 26 ML63611 User’s Manual Chapter 1 Overview Table 1-3 Pin Description (Basic Functions) (continued) Classification Pad No. Function name These pins can be selected as LCD segment signal output pins (L0 to L3) or common signal output pins by the mask option.
  • Page 27 ML63611 User’s Manual Chapter 1 Overview Table 1-3 Pin Description (Basic Functions) (continued) Classification Pad No. Function name Output pins dedicated to the LCD segment signal (L40 to L63). Resistance temperature sensor connection pin (for channel 0) Resistance/capacitance temperature sensor connection...

  • Page 28: Descriptions Of The Secondary Functions Of Each Pin

    ML63611 User’s Manual Chapter 1 Overview 1.7.2 Descriptions of the Secondary Functions of Each Pin The secondary functions of each pin of the ML63611 are listed in Table 1-4. Table 1-4 Pin Description (Secondary Functions) Classification Pin name Pad No.

  • Page 29: Handling Of Unused Pins

    ML63611 User’s Manual Chapter 1 Overview 1.7.3 Handling of Unused Pins Table 1-5 shows how unused pins should be handled. Table 1-5 Handling of Unused Pins Recommended pin handling OSC0, OSC1 Open , HC1, HC2 Open TST1, TST2 Connect to V P0.0 to P0.3...

  • Page 30: Basic Timing

    ML63611 User’s Manual Chapter 1 Overview Basic Timing 1.8.1 Basic Timing of CPU Operation The low-speed oscillation clock from the XT0/XT1 pins or the high-speed oscillation clock from the OSC0/OSC1 pins are used without frequency division as the system clock (CLK). The system clock signal is in phase with the signal from the XT1 pin or the OSC1 pin.
  • Page 31 ML63611 User’s Manual Chapter 1 Overview Output instruction Input instruction Instruction (example) MOV obj,(data A) MOV A,obj Output pin (data A) Input pin (data B) Accumulator (data B) Figure 1-7 Port I/O Basic Timing Notes: Regarding input signals “0” will be captured in the internal register if a “L” level is input to the input pin even once ( of Figure 1-8) during the data capture interval.

  • Page 32: Interrupt Basic Timing

    ML63611 User’s Manual Chapter 1 Overview 1.8.3 Interrupt Basic Timing Figure 1-9 shows the basic interrupt timing. As shown in the figure, when an interrupt factor is generated, the interrupt factor is sampled at the falling edge of CLK and an interrupt request (IRQ) is set at the first half of S1.

  • Page 33: Chapter 2. Cpu And Memory Spaces

    Chapter 2 CPU and Memory Spaces...

  • Page 34: Overview

    2. CPU and Memory Spaces Overview The ML63611 is equipped with Oki’s original CPU core nX-4/250. The instruction set of the nX-4/250 core consists of 407 types of instructions. The memory space consists of a 16-bit wide program memory space and a 4-bit wide data memory space. A stack for saving the program counter during a subroutine call or interrupt (call stack) and a stack for saving registers during a PUSH instruction (register stack) are provided separately from the memory space.

  • Page 35: Zero Flag (Z)

    ML63611 User’s Manual Chapter 2 CPU and Memory Spaces 2.2.2.2 Zero Flag (Z) The zero flag (Z) is a 1-bit flag that is set to “1” when the contents of the accumulator (A) are loaded with “0H”. The zero flag is set to “0” when the contents of the accumulator (A) are loaded with a value other than “0H”.

  • Page 36: Current Bank Register (Cbr), Extra Bank Register (Ebr), Hl Register (Hl), Xy Register (Xy)

    ML63611 User’s Manual Chapter 2 CPU and Memory Spaces 2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR), HL Register (HL), XY Register (XY) The CBR, EBR, HL, and XY registers are used for indirect addressing of data memory. The CBR and EBR registers indicate the data memory bank. The HL and XY registers indicate addresses in the bank.

  • Page 37: Program Counter (Pc)

    ML63611 User’s Manual Chapter 2 CPU and Memory Spaces 2.2.5 Program Counter (PC) The program counter (PC) is a counter with 16 valid bits that specifies the program memory space. 2.2.6 RA Registers (RA3, RA2, RA1, RA0) The RA registers are used for indirect program memory addressing (ROM table reference instructions).

  • Page 38: Stack Pointer (Sp) And Call Stack

    ML63611 User’s Manual Chapter 2 CPU and Memory Spaces 2.2.7 Stack Pointer (SP) and Call Stack The stack pointer (SP) is a pointer that indicates the call stack address where the program counter is saved when a subroutine call or interrupt occurs.

  • Page 39: Register Stack Pointer (Rsp) And Register Stack

    ML63611 User’s Manual Chapter 2 CPU and Memory Spaces 2.2.8 Register Stack Pointer (RSP) and Register Stack The register stack pointer (RSP) is a pointer that indicates the register stack address for saving various registers. RSP is a 4-bit up/down counter that is incremented during stack saves (execution of PUSH instructions) and is decremented during stack restores (execution of POP instructions).

  • Page 40: Memory Spaces

    ML63611 User’s Manual Chapter 2 CPU and Memory Spaces Memory Spaces 2.3.1 Program Memory Space The program memory space is the read-only memory that stores program data. The program memory space has a data length of 16 bits and extends from address 0000H to address 1FFFH.

  • Page 41: Data Memory Space

    ML63611 User’s Manual Chapter 2 CPU and Memory Spaces 2.3.2 Data Memory Space The data memory space contains data RAM and special function registers (SFRs). The data memory consists of 10 banks. One bank unit is 256 nibbles. BANK 0 is allocated as a SFR area, BANK 1 as the LCD display register, and BANK 2 and the following BANKS are data RAM.

  • Page 42: Chapter 3. Cpu Control Functions

    Chapter 3 CPU Control Functions...

  • Page 43: Overview

    ML63611 User’s Manual Chapter 3 CPU Control Functions 3. CPU Control Functions Overview Operating states, including system reset, are classified as follows. • Normal operation mode • System reset mode • Halt mode Figure 3-1 shows the CPU operating state transition diagram.

  • Page 44: System Reset Mode (Rst)

    System Reset Mode (RST) 3.2.1 Transfer to and State of System Reset Mode The ML63611 transfers to the system reset mode due to the following three causes: (1) When the RESET pin is taken to the “H” level When recognizing the reset signal, the signal input to the RESET signal is being sampled at 2 kHz.
  • Page 45 ML63611 User’s Manual Chapter 3 CPU Control Functions RESET0 Crystal oscillation 32.768 kHz output 125 ms RESETS CPU start Figure 3-3 Signals When System Reset is Generated Figure 3-4 shows the timing of transferring to the system reset mode when there is simultaneous key depression at the input Port 0.

  • Page 46: Halt Mode

    ML63611 User’s Manual Chapter 3 CPU Control Functions Halt Mode 3.3.1 Transfer to and State of Halt Mode Transfer to the halt mode is performed by the software when a HALT instruction is executed. When a HALT instruction is executed, the CPU enters the HALT mode at the S2 state of the HALT instruction.

  • Page 47: Halt Mode Release

    ML63611 User’s Manual Chapter 3 CPU Control Functions 3.3.2 Halt Mode Release The following two methods are available to release the halt mode. • Release by interrupt generation (transfer to normal operation mode) • Release by RESET pin (transfer to system reset mode) 3.3.2.1...

  • Page 48: Melody Data Interrupt And Halt Mode Release

    ML63611 User’s Manual Chapter 3 CPU Control Functions 3.3.3 Melody Data Interrupt and Halt Mode Release The halt mode is not released by a melody data interrupt. The melody data interrupt is different from a conventional interrupt in that the melody data interrupt is a hardware processing interrupt used for transfer of melody data to the melody circuit.

  • Page 49: Chapter 4. Interrupt (Int)

    Chapter 4 Interrupt (INT)

  • Page 50: Overview

    4. Interrupt (INT) Overview The ML63611 supports 18 interrupt factors: 4 external interrupts and 14 internal interrupts. With the exception of the watchdog timer interrupt, interrupt enable/disable is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE0 to IE4). Watchdog timer interrupt is a non- maskable interrupt.
  • Page 51 ML63611 User’s Manual Chapter 4 Interrupt (INT) Master interrupt enable flag Interrupt request Interrupt request Interrupt enable registers registers signals IRQ0 IRQ0.0 QWDT WDTINT IE0.1 IRQ0.1 MDINT IE0.2 IRQ0.2 EXI0 XI0INT QXI0 IE0.3 IRQ0.3 XI1INT QXI1 EXI1 IRQ1 IE1.0 IRQ1.0...

  • Page 52: Interrupt Registers

    ML63611 User’s Manual Chapter 4 Interrupt (INT) Interrupt Registers The following three types of registers are used to control interrupts. (1) Master interrupt enable register (MIEF) (2) Interrupt enable registers (IE0 to IE4) (3) Interrupt request registers (IRQ0 to IRQ4) These registers are described below.
  • Page 53 ML63611 User’s Manual Chapter 4 Interrupt (INT) (2) Interrupt enable registers (IE0 to IE4) IE0, IE1, IE2, IE3, and IE4 are registers that consist of 4 bits each. A logical AND of the corresponding bits of an interrupt enable register (IE0 to IE4) and an interrupt request register (IRQ0 to IRQ4) determines whether or not each interrupt request is issued to the CPU.
  • Page 54 ML63611 User’s Manual Chapter 4 Interrupt (INT) bit 3 bit 2 bit 1 bit 0 IE2 (052H) ETM3 ETM2 ETM1 ETM0 (R/W) Timer 3 interrupt enable flag 0: Disable (initial value) 1: Enable Timer 2 interrupt enable flag 0: Disable (initial value)
  • Page 55 ML63611 User’s Manual Chapter 4 Interrupt (INT) (3) Interrupt request registers (IRQ0 to IRQ4) IRQ0, IRQ1, IRQ2, IRQ3 and IRQ4 are registers that consist of 4 bits each. When an interrupt request is generated, the corresponding bit of the interrupt request register is set to “1” in the first half of the S1 state of the next instruction.
  • Page 56 ML63611 User’s Manual Chapter 4 Interrupt (INT) bit 1: QMD (reQuest Melody Driver) Melody end interrupt request flag. Melody end interrupts are generated when the melody driver outputs the end note data (END bit = “1”). bit 0: QWDT (reQuest WatchDog Timer) Watchdog timer interrupt request flag.
  • Page 57 ML63611 User’s Manual Chapter 4 Interrupt (INT) bit 3 bit 2 bit 1 bit 0 IRQ2 (057H) QTM3 QTM2 QTM1 QTM0 (R/W) Timer 3 interrupt request flag 0: No request (initial value) 1: Request Timer 2 interrupt request flag 0: No request (initial value)
  • Page 58 ML63611 User’s Manual Chapter 4 Interrupt (INT) bit 3 bit 2 bit 1 bit 0 IRQ3 (058H) Q10Hz — (R/W) 10 Hz interrupt request flag 0: No request (initial value) 1: Request Serial port transmit interrupt request flag 0: No request (initial value)
  • Page 59 ML63611 User’s Manual Chapter 4 Interrupt (INT) bit 3 bit 2 bit 1 bit 0 IRQ4 (059H) Q2Hz Q4Hz Q16Hz Q32Hz (R/W) 2 Hz interrupt request flag 0: No request (initial value) 1: Request 4 Hz interrupt request flag 0: No request (initial value)

  • Page 60: Interrupt Sequence

    ML63611 User’s Manual Chapter 4 Interrupt (INT) Interrupt Sequence 4.3.1 Interrupt Processing While MIE is “1”, operation transfers to interrupt processing when individual interrupt factors are generated. The watchdog timer interrupt is non-maskable and regardless of the MIE flag status, operation will shift to interrupt processing when the watchdog timer interrupt factor is generated.

  • Page 61: Return From An Interrupt Routine

    ML63611 User’s Manual Chapter 4 Interrupt (INT) 4.3.2 Return from an Interrupt Routine Return from a watchdog timer interrupt routine is performed with an “RTNMI” instruction. Return from all other interrupt routines is performed with an “RTI” instruction. Execution of “RTI” and “RTNMI” instructions both require 1 machine cycle.

  • Page 62: Chapter 5. Clock Generator Circuit (Osc)

    Chapter 5 Clock Generator Circuit (OSC)

  • Page 63: Overview

    5. Clock Generator Circuit (OSC) Overview The ML63611 has built in it a low-speed clock generator circuit and a high-speed clock generator circuit, and the system clock that becomes the basic operating clock of the CPU section is controlled using the frequency control register (FCON).

  • Page 64: Low-Speed Clock Generator Circuit

    ML63611 User’s Manual Chapter 5 Clock Generator Circuit (OSC) Low-Speed Clock Generator Circuit The low-speed clock generator circuit is configured using a crystal oscillator circuit. A crystal unit (32.768 kHz) is connected between the pins XT0 and XT1, and a capacitor (5 to 25 pF) is connected between the pins XT0 and .

  • Page 65: High-Speed Clock Generator Circuit

    ML63611 User’s Manual Chapter 5 Clock Generator Circuit (OSC) High-Speed Clock Generator Circuit The high-speed clock generator circuit has two modes, the RC oscillation mode and ceramic oscillation mode. In the OPTION A and OPTION B, only the RC oscillation mode is available. Oscillation modes are set by OSCSEL (bit 2 of FCON).
  • Page 66 ML63611 User’s Manual Chapter 5 Clock Generator Circuit (OSC) Table 5-2 lists typical values of oscillation frequency when the high-speed side RC oscillation mode is selected. Table 5-3 lists example external components to be attached when the high-speed side ceramic oscillation mode is selected.

  • Page 67: System Clock Control

    ML63611 User’s Manual Chapter 5 Clock Generator Circuit (OSC) System Clock Control The system clock is the basic operation clock of the CPU. The clock can be selected as follows with the CPUCLK (bit 0 of FCON) setting. • CPUCLK = “0” (initial value) The output of the low-speed clock generator circuit (TBCCLK) is the system clock.

  • Page 68: Frequency Control Register (Fcon)

    ML63611 User’s Manual Chapter 5 Clock Generator Circuit (OSC) Frequency Control Register (FCON) FCON is a special function register (SFR) that selects the system clock. bit 3 bit 2 bit 1 bit 0 FCON (062H)  OSCSEL ENOSC CPUCLK (R/W)

  • Page 69: System Clock Select Timing

    ML63611 User’s Manual Chapter 5 Clock Generator Circuit (OSC) System Clock Select Timing After system reset, the system clock is TBCCLK. When high-speed operation is necessary, switch the system clock to HSCLK. A flowchart of system clock operation is shown below.
  • Page 70 ML63611 User’s Manual Chapter 5 Clock Generator Circuit (OSC) When ENOSC (bit 1 of FCON) is set to “1”, oscillation starts in the mode selected by OSCSEL. At the same time, the internal logic power supply (V ) switches from the voltage regulator circuit (V/R1) output level (approx. 1.15 V) to the V level.

  • Page 71: Chapter 6. Time Base Counter (Tbc)

    Chapter 6 Time Base Counter (TBC)

  • Page 72: Overview

    ML63611 User’s Manual Chapter 6 Time Base Counter (TBC) 6. Time Base Counter (TBC) Overview The time base counter (TBC) is a 15-bit internal counter, which generates the clock supplied to internal peripheral functions. The TBC clock is a time base clock (TBCCLK).

  • Page 73: Time Base Counter Registers

    ML63611 User’s Manual Chapter 6 Time Base Counter (TBC) Time Base Counter Registers Time base counter register 0 (TBCR0), time base counter register 1 (TBCR1) These 4-bit special function registers (SFRs) are used to read the 1 to 8 Hz and 16 to 128 Hz outputs of the time base counter.
  • Page 74 ML63611 User’s Manual Chapter 6 Time Base Counter (TBC) 6 – 3 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias circuit for LCD bias...

  • Page 75: Chapter 7. Timers (Timer)

    Chapter 7 Timers (TIMER)

  • Page 76: Overview

    7. Timers (TIMER) Overview The ML63611 has four internal 8-bit timers (0 to 3). Timers 0 and 1, or timers 2 and 3, can be used in tandem as a 16-bit timer. Timers 0 and 1 have three operation modes: auto-reload mode, capture mode and frequency measurement mode.
  • Page 77 ML63611 User’s Manual Chapter 7 Timers (TIMER) Data bus TBCCLK overflow TM1CK TM1INT Control TM1CL TM1CH HSCLK PB.3/T13CK circuit TM0 overflow Capture Reload TM1CK PB.1/ Capture TM1DL TM1DH PB.1/ control circuit TM1CAP TM1OVF TM1CAP RESETS Inside the IC Inside the IC...

  • Page 78: Timer Registers

    ML63611 User’s Manual Chapter 7 Timers (TIMER) Timer Registers The following four types of registers are used for timer control. (1) Timer data registers (TM0DL, TM0DH, TM1DL, TM1DH, TM2DL, TM2DH, TM3DL, TM3DH) (2) Timer counter registers (TM0CL, TM0CH, TM1CL, TM1CH, TM2CL, TM2CH, TM3CL, TM3CH)
  • Page 79 ML63611 User’s Manual Chapter 7 Timers (TIMER) Timer 2 Registers bit 3 bit 2 bit 1 bit 0 TM2DL (076H) T2D3 T2D2 T2D1 T2D0 (Timer 2 lower) (R/W) bit 3 bit 2 bit 1 bit 0 TM2DH (077H) T2D7 T2D6...
  • Page 80 ML63611 User’s Manual Chapter 7 Timers (TIMER) Timer 1 Registers bit 3 bit 2 bit 1 bit 0 TM1CL (06EH) T1C3 T1C2 T1C1 T1C0 (Timer 1 lower) (R/W) bit 3 bit 2 bit 1 bit 0 TM1CH (06FH) T1C7 T1C6...
  • Page 81 ML63611 User’s Manual Chapter 7 Timers (TIMER) (3) Timer control registers (TM0CON0, TM0CON1, TM1CON0, TM1CON1, TM2CON0, TM2CON1, TM3CON0, TM3CON1) • Timer control registers select the operation mode and clock for each timer. • At system reset, all valid bits are cleared to “0”.
  • Page 82 ML63611 User’s Manual Chapter 7 Timers (TIMER) bit 3 bit 2 bit 1 bit 0   TM0CON1 (071H) TM0CL1 TM0CL0 (R/W) Timer 0 clock select bit 1 bit 0 TBCCLK (initial value) HSCLK (high-speed clock) External clock Not used bit 1, 0: TM0CL1, TM0CL0 These bits select the timer 0 clock.
  • Page 83 ML63611 User’s Manual Chapter 7 Timers (TIMER) Timer 1 Registers bit 3 bit 2 bit 1 bit 0 TM1CON0 (072H)   TM1ECAP TM1RUN (R/W) Timer 1 mode select bit 1 bit 0 Auto-reload mode stop or 16-bit timer mode (initial value)
  • Page 84 ML63611 User’s Manual Chapter 7 Timers (TIMER) Timer 2 Registers To use timer 3 in combination as a 16-bit timer, set timer 3 control registers TM3CON0 and TM3CON1. bit 3 bit 2 bit 1 bit 0 TM2CON0 (07EH)  ...
  • Page 85 ML63611 User’s Manual Chapter 7 Timers (TIMER) Timer 3 Registers bit 3 bit 2 bit 1 bit 0 TM3CON0 (080H)    TM3RUN (R/W) Timer 3 mode select Auto-reload mode stop or 16-bit timer mode (initial value) Auto-reload mode operation bit 0: TM3RUN This bit selects the timer 3 operation mode.
  • Page 86 ML63611 User’s Manual Chapter 7 Timers (TIMER) (4) Timer status registers (TM0STAT, TM1STAT, TM2STAT, TM3STAT) • Timer status registers read the status of each timer. • At system reset, all valid bits are cleared to “0”. Timer 0 Registers bit 3...
  • Page 87 ML63611 User’s Manual Chapter 7 Timers (TIMER) bit 1: TM1CAP (TiMer1 CAPture) This bit indicates whether or not new capture data is present. When TM1CAP = “0”: A value of “0” indicates that there has been no new capture data since system reset or since the last time TM1CAP was read.
  • Page 88 ML63611 User’s Manual Chapter 7 Timers (TIMER) [Supplement] List of Timer Registers Timer 0 Registers Name Symbol Address Initial value Timer 0 data register L TM0DL 068H Timer 0 data register H TM0DH 069H Timer 0 counter register L TM0CL...
  • Page 89 ML63611 User’s Manual Chapter 7 Timers (TIMER) Timer Operation 7.4.1 Timer Clock The timer clock can be selected as TBCCLK (low-speed clock: 32.768 kHz), HSCLK (high-speed clock), or an external clock. By using timer 0 and timer 2 overflow signals as clocks for timer 1 and timer 3, respectively, the timers can be used in pairs as 16-bit timers.

  • Page 90: Timer Interrupt Requests And Overflow Flags

    ML63611 User’s Manual Chapter 7 Timers (TIMER) 7.4.4 Timer Interrupt Requests and Overflow Flags Timers generate timer interrupt requests when the timer counter register overflows. The overflow flag toggles between “1” and “0” at each overflow. The output of the overflow flag of timers 0 and 1 can be output to secondary port functions PB.0/TM0OVF and PB.1/TM1OVF pins.

  • Page 91: Auto-Reload Mode Operation

    ML63611 User’s Manual Chapter 7 Timers (TIMER) 7.4.5 Auto-Reload Mode Operation Timers 0 to 3 can be used as auto-reload mode timers. The setup method is as follows. • Timer 0: Set FMEAS0 (bit 2 of TM0CON0) to “0”, and set TM0ECAP (bit 1 of TM0CON0) to “0”.
  • Page 92 ML63611 User’s Manual Chapter 7 Timers (TIMER) The operation procedures are as follows. Set PB.1 to the output mode (TM1OVF) secondary function. Write 534FH to the timer data and timer counter registers. TM1DH = TM1CH = 5H (bits 15–12) TM1DL = TM1CL = 3H (bits 11–8)

  • Page 93: Capture Mode Operation

    ML63611 User’s Manual Chapter 7 Timers (TIMER) 7.4.6 Capture Mode Operation Timer 0 and timer 1 can be used as capture mode timers. In a capture mode, a change in the capture input (PB.0/TM0CAP, PB.1/TM1CAP) level during operation of the timer counter register triggers loading of the value of the timer counter register into the timer data register.
  • Page 94 ML63611 User’s Manual Chapter 7 Timers (TIMER) The operation procedure is listed below. Set PB.0/TM0CAP to input mode, and enable XI0INT and TM0INT. Clear all bits of the timer counter registers and timer data registers to zero. Set TM0CON0 to the capture mode, and set TM0RUN to “1” to begin upward counting.
  • Page 95 ML63611 User’s Manual Chapter 7 Timers (TIMER) CAPT PB.0/TM0CAP input Timer clock TM0ECAP TM0CAP Figure 7-10 Capture Signal (CAPT) Generator Circuit Note: Set the pulse width of the capture trigger signal to be input to more than or equal to two cycles of the timer clock.

  • Page 96: Frequency Measurement Mode Operation

    ML63611 User’s Manual Chapter 7 Timers (TIMER) 7.4.7 Frequency Measurement Mode Operation The frequency measurement mode is used to measure the frequency of the RC oscillator clock, which has wide product variation. Timers 0 and 1, and timers 2 and 3 can be used in the frequency measurement mode. These timers are set as follows for the frequency measurement mode: •...
  • Page 97 ML63611 User’s Manual Chapter 7 Timers (TIMER) Assuming that the ceramic oscillation clock is exactly 700 kHz, value N1 read from the timer counter register is: N1 = 700000 × 437/32768 = 9335 (decimal) = 2477 (hexadecimal) = 0010 0100...
  • Page 98 ML63611 User’s Manual Chapter 7 Timers (TIMER) Figure 7-12 illustrates the operation of baud ratae clock for an RC oscillator clock frequency of 600 kHz. FFFF FFC2 TM3CH TM3CL TM2CH TM2CL 0000 TM3DH, TM3DL FFC2 TM2DH, TM2DL TM3INT (9677 Hz) 0.10333 ms...
  • Page 99 Chapter 8 100 Hz Timer Counter (100HzTC)

  • Page 100: Chapter 8. 100 Hz Timer Counter (100Hztc)

    ML63611 User’s Manual Chapter 8 100 Hz Timer Counter (100HzTC) 8. 100 Hz Timer Counter (100HzTC) Overview The 100 Hz timer counter has a circuit that divides the TBC6 output (512 Hz) of the time base counter to generate a 10 Hz interrupt. The 100 Hz timer consists of a 5/6-base counter and two decimal counters.

  • Page 101: 100 Hz Timer Counter Registers

    ML63611 User’s Manual Chapter 8 100 Hz Timer Counter (100HzTC) 100 Hz Timer Counter Registers (1) 100 Hz timer counter control register (T100CON) This is a 4-bit special function register (SFR) controlling the 100 Hz timer counter. bit 3 bit 2...

  • Page 102: 100 Hz Timer Counter Operation

    ML63611 User’s Manual Chapter 8 100 Hz Timer Counter (100HzTC) 100 Hz Timer Counter Operation The 100 Hz timer counter begins counting when bit 0 (ECNT) of the 100 Hz timer counter control register (T100CON) is set to “1”. The 512 Hz output of the time base counter is divided into 100 Hz by the 5/6-base counter.

  • Page 103: Chapter 9. Watchdog Timer (Wdt)

    Chapter 9 Watchdog Timer (WDT)

  • Page 104: Overview

    ML63611 User’s Manual Chapter 9 Watchdog Timer (WDT) 9. Watchdog Timer (WDT) Overview The watchdog timer is a circuit to detect CPU malfunction. The WDT consists of a 9-bit watchdog timer counter (WTDC) counting the 256 Hz output of the TBC7 of the time base counter (TBC), and a watchdog timer control register (WDTCON) to start and clear WDTC.

  • Page 105: Watchdog Timer Control Register (Wdtcon)

    ML63611 User’s Manual Chapter 9 Watchdog Timer (WDT) Watchdog Timer Control Register (WDTCON) The watchdog timer control register (WDTCON) is a 4-bit write-only special function register (SFR) used to start/clear the watchdog timer counter (WDTC). bit 3 bit 2 bit 1...
  • Page 106 ML63611 User’s Manual Chapter 9 Watchdog Timer (WDT) Figure 9-2 shows a flowchart of watchdog timer processing. WDT operation is stopped System reset Internal pointer “0” Write “5H” Internal pointer “0” → “1” to WDTCON Write “0AH” WDT operation is started to WDTCON Internal pointer “1”...
  • Page 107 ML63611 User’s Manual Chapter 9 Watchdog Timer (WDT) Figure 9-3 shows the timing chart for watchdog timer operation. Fault occurrence ↓ System reset Data: WDTCON write signal Internal pointer Overflow Watchdog timer counter (WDTC) content 1.9 to 2.0 s Start...

  • Page 108: Chapter 10. Ports (Input, I/O Port)

    Chapter 10 Ports (INPUT, I/O PORT)

  • Page 109: Overview

    Overview The ML63611 has built in it a 4-bit input-only port (Port 0) and 8-bit I/O ports (Port A, Port B, Port C, and Port Port 0 has the three modes of input with pull-up resistor, input with pull-down resistor, and high impedance, one of which can be selected by software.

  • Page 110: Port 0 (P0.0-P0.3)

    10.3 Port 0 (P0.0–P0.3) The ML63611 has Port 0, a 4-bit input-only port. Apart from the input port function, Port 0 has the functions of external interrupts and the function of transfer to system reset due to simultaneous key depression.
  • Page 111 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (2) Port 0 control registers 0/1 (P0CON0, P0CON1) P0CON0 and P0CON1 are 4-bit special function registers (SFRs) that select pull-up or pull-down resistors and select the external interrupt sampling frequency of Port 0 secondary function.
  • Page 112 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (3) Port 0 interrupt enable register (P0IE) P0IE is a 4-bit special function register (SFR) that enables/disables individual bits when port 0 is used as an external interrupt. At system reset, all bits in the port interrupt enable register are cleared to “0” and port 0 is initialized to the interrupt disabled state.

  • Page 113: Port 0 External Interrupt Function (External Interrupt 5)

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.3.3 Port 0 External Interrupt Function (External Interrupt 5) Port 0 has external interrupt 5 allocated as secondary function. Individual bits can be enabled/disabled for external interrupt 5. External interrupt generation for each input of port 0 is triggered by the falling edge of either the 128 Hz or 4 kHz sampling clock from the time base counter.
  • Page 114 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 128 Hz or 4 kHz P0.0 P0.1 P0.2 P0.3 XI5INT QXI5 (a) When P0PUD = “0” 128 Hz or 4 kHz P0.0 P0.1 P0.2 P0.3 XI5INT QXI5 (b) When P0PUD = “1”...

  • Page 115: Port A (Pa.0-Pa.3)

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.4 Port A (PA.0–PA.3) The ML63611 has Port A, a 4-bit input/output port. 10.4.1 Port A Configuration The circuit configuration for port A is shown in Figure 10-4. Data bus Output...

  • Page 116: Port A Registers

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.4.2 Port A Registers (1) Port A data register (PAD) PAD is a 4-bit special function register (SFR) used to set the output values for the port. When a bit in the port direction register (PADIR) is set to “1” to select the output mode, the content of the corresponding bit in the port data register (PAD) is output to the port (port A).
  • Page 117 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (2) Port A direction register (PADIR) PADIR is a 4-bit special function register (SFR) which specifies the port input/output direction for each bit. Pins corresponding to PADIR bits set to “0” are input, and those corresponding to bits set to “1” are output.
  • Page 118 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (3) Port A control registers 0/1 (PACON0, PACON1) PACON0 and PACON1 are 4-bit special function registers (SFRs) used to select port input/output mode. The input mode may be pull-down resistor input, pull-up resistor input or high-impedance input.

  • Page 119: Port B (Pb.0-Pb.3)

    Chapter 10 Ports (INPUT, I/O PORT) 10.5 Port B (PB.0–PB.3) The ML63611 has Port B, a 4-bit input/output port. 10.5.1 Port B Configuration As its I/O port functions, port B has the input mode that can be pull-up resistor input, pull-down resistor input, or high-impedance input and the output mode that can be P-channel open drain output, N-channel open drain output, CMOS output, or high-impedance output.

  • Page 120: Port B Registers

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.5.2 Port B Registers The following registers are used to control port B: (1) Port B data register (PBD) (2) Port B direction register (PBDIR) (3) Port B control registers 0/1 (PBCON0, PBCON1)
  • Page 121 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (2) Port B direction register (PBDIR) PBDIR is a 4-bit special function register (SFR) which specifies the port input/output direction for each bit. Pins corresponding to PBDIR bits set to “0” are input, and those corresponding to PBDIR bits set to “1” are output.
  • Page 122 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (3) Port B control registers 0/1 (PBCON0, PBCON1) PBCON0 and PBCON1 are 4-bit special function registers (SFRs) used to select port input/output mode. The input mode can be pull-down resistor input, pull-up resistor input or high-impedance input.
  • Page 123 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (4) Port B mode register (PBMOD) PBMOD is a 4-bit special function register (SFR) used to select the sampling frequency when port B is used as an external interrupt. It is also used to select port B secondary functions other than external interrupt.
  • Page 124 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (5) Port B interrupt enable register (PBIE) PBIE is a 4-bit special function register (SFR) that enables/disables individual bits when port B is used as an external interrupt input. At system reset, all bits in PBIE are cleared to “0” and port B is initialized to the interrupt disabled state.

  • Page 125: Port B External Interrupt Function (External Interrupt 0)

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.5.3 Port B External Interrupt Function (External Interrupt 0) Port B has external interrupt 0 allocated as secondary function. Individual bits can be enabled/disabled for external interrupt 0. External interrupt generation for port B is triggered by the falling edge of the 128 Hz or 4 kHz time base counter, which is the sampling clock.
  • Page 126 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 128 Hz or 4 kHz PB.0 PB.1 PB.2 PB.3 XI0INT QXI0 (a) When PB0MD1 to PB3MD1 = “0” 128 Hz or 4 kHz PB.0 PB.1 PB.2 PB.3 XI0INT QXI0 (b) When PB0MD1 and PB1MD1 = “0” and PB2MD1 and PB3MD = “1”...

  • Page 127: Port C (Pc.0-Pc.3)

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.6 Port C (PC.0–PC.3) The ML63611 has Port C, a 4-bit input/output port. 10.6.1 Port C Configuration The circuit configuration for port C is shown in Figure 10-10. Data bus Output...

  • Page 128: Port C Registers

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.6.2 Port C Registers (1) Port C data register (PCD) PCD is a 4-bit special function register used to set the output values for port C. When a bit in the port C direction register (PCDIR) is set to “1” to select the output mode, the content of the corresponding bit in the port C data register is output to the port C.
  • Page 129 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (3) Port C control registers 0/1 (PCCON0, PCCON1) PCCON0 and PCCON1 are 4-bit special function registers (SFRs) used to select port input/output mode. The input mode can be pull-down resistor input, pull-up resistor input or high-impedance input.
  • Page 130 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (4) Port C mode registers 0/1 (PCMOD0, PCMOD1) PCMOD0 and PCMOD1 are 4-bit special function registers (SFRs) used to select the sampling frequency when ports are used for external interrupt, and to select secondary functions other than external interrupt.
  • Page 131 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) bit 3 bit 2 bit 1 bit 0 PCMOD0 (037H)    (R/W) External interrupt sampling frequency select 0: 128 Hz sampling (initial value) 1: 4 kHz sampling bit 3...
  • Page 132 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (5) Port C interrupt enable register (PCIE) PCIE is a 4-bit special function register (SFR) that enables/disables individual bits when port C is used as an external interrupt input. At system reset, all bits in PCIE are cleared to “0” and port C is initialized to the interrupt disabled state.

  • Page 133: Port C External Interrupt Function (External Interrupt 1)

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.6.3 Port C External Interrupt Function (External Interrupt 1) Port C has external interrupt 1 allocated as secondary function. Individual bits can be enabled/disabled for external interrupt 1. External interrupt generation for port C is triggered by the falling edge of the 128 Hz or 4 kHz time base counter, which is the sampling clock.
  • Page 134 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) • When either PC.0 or PC.1 input is at a “H” level OR either PC.2 or PC.3 input is at a “L” level External interrupt 1 is generated when both PC.0 and PC.1 inputs change to a “L” level AND both PC.2 and PC.3 inputs change to a “H”...

  • Page 135: Port E (Pe.0-Pe.3)

    10.7 Port E (PE.0–PE.3) The ML63611 has Port E, a 4-bit input/output port. Apart from the input/output port function, Port E has the functions of external interrupts, the function of RC oscillator clock output for an A/D converter, the low-speed clock output function, and the high-speed clock output function.

  • Page 136: Port E Registers

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.7.2 Port E Registers (1) Port E data register (PED) PED is a 4-bit special function register used to set the output values for port E. When a bit in the port E direction register (PEDIR) is set to “1” to select the output mode, the content of the corresponding bit in the port E data register is output to the port E.
  • Page 137 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (3) Port E control registers 0/1 (PECON0, PECON1) PECON0 and PECON1 are 4-bit special function registers (SFRs) used to select port input/output mode. The input mode can be pull-down resistor input, pull-up resistor input or high-impedance input.
  • Page 138 ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) (4) Port E mode register (PEMOD) PEMOD is a 4-bit special function register (SFR) used to select the sampling frequency when PE.3 is used as an external interrupt. It is also used to select port E secondary functions other than external interrupt.

  • Page 139: Port E.3 External Interrupt Function (External Interrupt 2)

    ML63611 User’s Manual Chapter 10 Ports (INPUT, I/O PORT) 10.7.3 Port E.3 External Interrupt Function (External Interrupt 2) Port E.3 has external interrupt 2 allocated as secondary function. External interrupt generation for PE.3 is triggered by the falling edge of the 128 Hz or 4 kHz time base counter, which is the sampling clock.

  • Page 140: Chapter 11. Melody Driver (Melody)

    Chapter 11 Melody Driver (MELODY)

  • Page 141: Overview

    11.1 Overview The ML63611 has an internal melody circuit and buzzer circuit. While automatically reading melody data in ROM (program memory) as specified by an MSA instruction, the melody circuit outputs a melody signal via the MD and MDB pins.

  • Page 142: Melody Driver Registers

    ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) 11.3 Melody Driver Registers (1) Tempo Register (TEMPO) TEMPO is a 4-bit special function register (SFR) that sets the tempo of the melody driver. bit 3 bit 2 bit 1 bit 0...
  • Page 143 ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) bit 3: MSF This flag indicates the melody output status. When an MSA instruction starts the melody, MSF is set to “1”. After output of the last melody data (END bit is “1”), MSF is cleared to “0”.

  • Page 144: Melody Circuit Operation

    ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) bit 1, 0: MBM1, MBM0 These bits select the buzzer output mode. Output of two types of intermittent tones, a single tone or a continuous tone can be selected. At system reset, MBM1 and MBM0 are cleared to “0”, selecting output of intermittent tone 1.

  • Page 145: Tempo Data

    ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) 11.4.1 Tempo Data Tempo data defines the basic tone length. Tempo data is set in the tempo register (TEMPO). The tempos (number of counts per minute) set by TEMPO are shown in Table 11-1.

  • Page 146: Melody Data

    ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) 11.4.2 Melody Data Melody data is 14-bit format data in the program ROM defining tone, tone length and end tone. The melody data format is indicated in Figure 13-3. bit 15 bit 14...
  • Page 147 ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) Table 11-2 Tone and Tone Code Correspondence (continued) Frequency Tone code Tone (Hz) N6–N0 1260 1338 1394 1490 1560 1680 1771 1872 1986 2114 2341 2521 2621 2979 (2) Tone length code The tone length code is set in melody data bits 13 through 8.
  • Page 148 ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) Table 11-3 Tone Length and Tone Length Code Correspondence Tone length code Tone length L5–L0 Tone lengths specified by the tone length code and the tempo data are expressed by the following: 1.953125 ×...

  • Page 149: Melody Circuit Application Example

    ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) 11.4.3 Melody Circuit Application Example An example melody is shown in Figure 11-4. Table 11-4 lists the note codes for the melody shown in Figure 11-4. = 120 Figure 11-4 Example Melody...

  • Page 150: Buzzer Circuit Operation

    ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) 11.5 Buzzer Circuit Operation When EMBD (bit 2 of MDCON) is set to “1”, a buzzer driver signal is sent to the melody driver output pins (MD, MDB). Four buzzer output modes can be selected by MBM1 (bit 1 of MDCON) and MBM0 (bit 0 of MDCON): two types of intermittent tones, a single tone, or a continuous tone output.
  • Page 151 ML63611 User’s Manual Chapter 11 Melody Driver (MELODY) EMBD 8 Hz Output MD (a) MBM1 = “0”, MBM0 = “0” (intermittent tone 1) EMBD 8 Hz 1 Hz Output MD (b) MBM1 = “0”, MBM0 = “1” (intermittent tone 2)

  • Page 152: Chapter 12. Serial Port (Sio)

    Chapter 12 Serial Port (SIO)

  • Page 153: Overview

    12. Serial Port (SIO) 12.1 Overview The ML63611 has a built-in serial communication port (serial port) for either synchronous or asynchronous communication. The serial port implements the send and receive circuits in independent circuits, making it possible to send and receive simultaneously.
  • Page 154 ML63611 User’s Manual Chapter 12 Serial Port (SIO) Figure 12-1 Serial Port Configuration 12 – 2 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias circuit for LCD bias...

  • Page 155: Serial Port Registers

    ML63611 User’s Manual Chapter 12 Serial Port (SIO) 12.3 Serial Port Registers (1) Send control registers 0/1 (STCON0, STCON1) STCON0 and STCON1 are 4-bit special function registers (SFRs) to control the serial port send operation. STCON0 and STCON1 are initialized to “0” at system reset.
  • Page 156 ML63611 User’s Manual Chapter 12 Serial Port (SIO) bit 3 bit 2 bit 1 bit 0 STCON1 (0A7H) STLMB STPOE STPEN STCLK (R/W) LSB/MSB head select 0 : Start from LSB (initial value) 1 : Start from MSB Odd/even parity select...
  • Page 157 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (2) Send buffer registers (STBUFL, STBUFH) bit 3 bit 2 bit 1 bit 0 STBUFL (0A4H) (R/W) bit 3 bit 2 bit 1 bit 0 STBUFH (0A5H) (R/W) STBUFL and STBUFH are 4-bit special function registers (SFRs) that set send data for serial port send operation.
  • Page 158 ML63611 User’s Manual Chapter 12 Serial Port (SIO) START Has send data been written to STBUFH ? BFULL←“1” Is interrupt generated or BFULL = 0? for 12-clock periods (6 instructions) delay 16 µsec at 700 kHz, when the CPU is...
  • Page 159 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (4) Receive control registers 0/1 (SRCON0, SRCON1) SRCON0 and SRCON1 are 4-bit special function registers (SFRs) controlling serial port receive operation. SRCON0 and SRCON1 are initialized to “0” at system reset. bit 3...
  • Page 160 ML63611 User’s Manual Chapter 12 Serial Port (SIO) bit 3 bit 2 bit 1 bit 0 SRCON1 (0ABH) SRLMB SRPOE SRPEN SRCLK (R/W) LSB/MSB head select 0 : Start at LSB (initial value) 1 : Start at MSB Odd/even parity select...
  • Page 161 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (5) Receive register The receive register is the shift register that handles shift operation at receive. It is initialized to 00H at system reset. It cannot be directly accessed by the CPU. When a receive operation is complete, the data read into the receive register is transferred to SRBUFL/H, and at the same time the receive interrupt request signal (SRINT) is generated.
  • Page 162 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (7) Receive baud rate setting register (SRBRT) SRBRT is a 4-bit special function register (SFR) used to set the receive baud rate for serial port receive operation in UART mode. SRBRT is initialized to 0CH at system reset.
  • Page 163 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (8) Serial port status register (SSTAT) SSTAT is a 4-bit special function register (SFR) used to indicate the status of serial port send/receive. SSTAT is initialized to “0” at system reset. SSTAT is a read-only register, and the content is reset every time it is read.

  • Page 164: Serial Port Operation Description

    ML63611 User’s Manual Chapter 12 Serial Port (SIO) 12.4 Serial Port Operation Description 12.4.1 Data Format (1) UART mode The data format for the UART mode is shown in Figure 12-3. SRCON0/1 and STCON0/1 can be set to specify a data bit length of 5 to 8 bits. The parity bit can be enabled/disabled.

  • Page 165: Send Operation Description

    ML63611 User’s Manual Chapter 12 Serial Port (SIO) 12.4.2 Send Operation Description The serial port send circuit has a two-stage configuration. This consists of the send register and the send buffer register (STBUFL/H), so it is possible to set send data to STBUFL/H while sending the previous data. When the BFULL flag of the serial port status register (SSTAT) is 1, however, it indicates that STBUFL/H send data has not yet been transferred to the send register.
  • Page 166 ML63611 User’s Manual Chapter 12 Serial Port (SIO) Figure 12-5 UART Mode Send Timing Chart 12 – 14 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias...
  • Page 167 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (2) Synchronous internal clock mode The synchronous internal clock mode is selected by setting STMOD (bit 0 of STCON0) to “1”, and STCLK (bit 0 of STCON1) to “1”. Figure 12-6 is the send timing chart for the synchronous internal clock mode.
  • Page 168 ML63611 User’s Manual Chapter 12 Serial Port (SIO) Figure 12-6 Send Timing Chart for Synchronous Internal Clock Mode 12 – 16 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias...
  • Page 169 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (3) Synchronous external clock mode The synchronous external clock mode is selected by setting STMOD (bit 0 of STCON0) to “1”, and STCLK (bit 0 of STCON1) to “0”. Figure 12-7 is the send timing chart for the synchronous external clock mode.
  • Page 170 ML63611 User’s Manual Chapter 12 Serial Port (SIO) Figure 12-7 Send Timing Chart for Synchronous External Clock Mode 12 – 18 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias...

  • Page 171: Receive Operation Description

    ML63611 User’s Manual Chapter 12 Serial Port (SIO) 12.4.3 Receive Operation Description (1) UART mode The UART mode is specified by setting SRMOD (bit 0 of SRCON0) to “0”. Figure 12-8 is the UART mode receive timing chart. The UART mode receive procedure is described below.
  • Page 172 ML63611 User’s Manual Chapter 12 Serial Port (SIO) Figure 12-8 UART Mode Receive Timing Chart 12 – 20 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias...
  • Page 173 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (2) Synchronous internal clock mode The synchronous internal clock mode is selected by setting SRMOD (bit 0 of SRCON0) to “1” and SRCLK (bit 0 of SRCON1) to “1”. Figure 12-9 is the receive timing chart for the synchronous internal clock mode.
  • Page 174 ML63611 User’s Manual Chapter 12 Serial Port (SIO) Figure 12-9 Synchronous Internal Clock Mode Receive Timing Chart 12 – 22 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias...
  • Page 175 ML63611 User’s Manual Chapter 12 Serial Port (SIO) (3) Synchronous external clock mode The synchronous external clock mode is selected by setting SRMOD (bit 0 of SRCON0) to “1” and SRCLK (bit 0 of SRCON1) to “0”. Figure 12-10 is the receive timing chart for the synchronous external clock mode.
  • Page 176 ML63611 User’s Manual Chapter 12 Serial Port (SIO) Figure 12-10 Synchronous External Clock Mode Receive Timing Chart 12 – 24 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator circuit for LCD bias...

  • Page 177: Send/Receive Data Lsb/Msb First Select

    ML63611 User’s Manual Chapter 12 Serial Port (SIO) 12.5 Send/Receive Data LSB/MSB First Select Either LSB first or MSB first for send can be selected by setting STLMB (bit 3 of STCON1). Either LSB first or MSB first for receive can be selected by setting SRLMB (bit 3 of SRCON1).

  • Page 178: Selecting Receive Data Lsb/Msb First

    ML63611 User’s Manual Chapter 12 Serial Port (SIO) 12.5.2 Selecting Receive Data LSB/MSB First When the LSB is first in receive data, set SRLMB (bit 3 of SRCON1) to “0”. If the MSB is first, set SRLMB to “1”. The correspondence between receive data and SRBUFL/H bits for LSB first receive is shown in Figure 12-13, and for MSB first receive in Figure 12-14.

  • Page 179: Chapter 13. Lcd Driver (Lcd)

    Chapter 13 LCD Driver (LCD)

  • Page 180: Overview

    13.1 Overview The ML63611 has built in it a segment type LCD driver (LCD) with 64 outputs. The LCD driver section consists of a segment register, the display control register 0 (DSPCON0), the display control register 1 (DSPCON1), the display contrast register (DSPCNT), the LCD driver circuits for 64 outputs, and the bias generator circuit (BIAS).

  • Page 181: Lcd Driver Configuration

    ML63611 User’s Manual Chapter 13 LCD Driver (LCD) 13.2 LCD Driver Configuration Figure 13-1 shows the LCD driver configuration of the OPTION B and OPTION D; Figure 13-2, the LCD driver configuration of the OPTION A; and Figure 13-3, the LCD driver configuration of OPTION C. Figures 13-4, 13-5, and 13-6 show the peripheral circuits of the LCD driver and segment register.
  • Page 182 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) Internal data bus Mask option DSPCON0/1, DSPCNT Segment register Timing generator circuit Inside the IC Bias generator circuit LCD driver circuit (64 lines) (BIAS) C2 V Figure 13-3 OPTION C LCD Driver Configuration 13 –...
  • Page 183 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) L4 to L31, L40 to L63 (SEG-only pins) LCD driver ΦLCD (frame clock) Common timing signal Segment register bit Data bus select WRAM SYSCLK ERAM BANK1 Segment register address select Figure 13-4 LCD Driver and Segment Register (Circuit configuration of SEG-only pins L14 to L31 and L40 to L63) 13 –...
  • Page 184 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) L0 to L3, L36 to L39 (SEG or COM pins) LCD driver ΦLCD (frame clock) Common timing signal Data bus Segment register bit select Common “1” “0” output select WRAM SYSCLK ERAM...
  • Page 185 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) L32 to L35 (SEG or output port pins) LCD driver PORT/SEG ΦLCD (frame clock) “1” Output port select (mask option) “0” Common timing signal Segment Data bus register bit select WRAM SYSCLK...

  • Page 186: Lcd Driver Registers

    ML63611 User’s Manual Chapter 13 LCD Driver (LCD) 13.3 LCD Driver Registers (1) Display control register 0 (DSPCON0) DSPCON0 is a 4-bit special function register (SFR) controlling LCD driver operation. bit 3 bit 2 bit 1 bit 0 DSPCON0 (090H)
  • Page 187 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) (2) Display control register 1 (DSPCON1) DSPCON1 is a 4-bit special function register (SFR) used to select the LCD driver duty. At system reset, bits 0 and 1 of DSPCON1 are initialized to “0”.
  • Page 188 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) (4) LP0 control register (LP0CON) LP0CON is a 4-bit special function register (SFR) used to determine the output mode when pins L32 to L35 are selected as output port pins by the mask option.

  • Page 189: Lcd Driver Operation

    ML63611 User’s Manual Chapter 13 LCD Driver (LCD) 13.4 LCD Driver Operation The LCD driver outputs LCD driving waveforms based on the data written to the segment register. Use the mask option to specify the assignment of segment register address and bit and to select the segment driver and common driver.

  • Page 190: Output Port Selection By Mask Option

    ML63611 User’s Manual Chapter 13 LCD Driver (LCD) 13.5 Output Port Selection by Mask Option The four pins L32 to L35 of the LCD driver can be selected by mask option setting to form an output port in 4-bit unit.

  • Page 191: Bias Generator Circuit (Bias)

    ML63611 User’s Manual Chapter 13 LCD Driver (LCD) 13.6 Bias Generator Circuit (BIAS) The bias generator circuit (BIAS) for the LCD driver in the OPTION B and OPTION D generates the different bias voltages, when external capacitors are connected, by multiplying the constant voltage output (V = 0.95 V)
  • Page 192 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) (2) Figure 13-9 shows the OPTION A bias generator configuration. (1.5 V) (4.5 V) 1 kHz (from time base counter) Bias (3.0 V) generator circuit (1.5 V) (0 V) To LCD driver...
  • Page 193 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) (3) Figure 13-10 shows the OPTION C bias generator configuration. (3.0 V) (4.5 V) 1 kHz (from time base counter) Bias (3.0 V) generator circuit (1.5 V) (0 V) To LCD driver...
  • Page 194 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) Table 13-2 OPTION B Display Contrast Adjusting Voltages (V (Ta = 25°C, V = 0 V) DSPCNT Voltage (V) Contrast CN3–0 Min. Typ. Max. 0.90 0.95 1.00 Light 0.93 0.98 1.03 0.96 1.01...
  • Page 195 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) Table 13-4 OPTION B and OPTION D Display Contrast Adjusting Voltages (V = 0 V) Voltage (V) BISEL Mode Power supply Min. Typ. Max. 2 × V Typ. – 0.3 Typ. + 0.3 1/3 bias 3 ×...

  • Page 196: Lcd Driver Output Waveform

    ML63611 User’s Manual Chapter 13 LCD Driver (LCD) 13.7 LCD Driver Output Waveform Figures 13-11 (a) and 13-11 (b) show the output waveforms for 1/4 duty and 1/3 bias, and Figures 13-12 (a) and 13-12 (b) show the output waveforms for 1/3 duty and 1/3 bias.
  • Page 197 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) Frame frequency 64 Hz COM1 series: OFF COM2 series: OFF COM3 series: OFF COM4 series: OFF COM1 series: ON COM2 series: OFF COM3 series: OFF COM4 series: OFF COM1 series: OFF COM2 series: ON...
  • Page 198 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) Frame frequency 85.3 Hz COM1 COM2 COM3 Figure 13-12 (a) 1/3 Duty, 1/3 Bias Common Output Waveform 13 – 19 OPTION A (C): 1.5 V (3.0 V), Without regulator OPTION B (D): 1.5 V (3.0 V), With regulator...
  • Page 199 ML63611 User’s Manual Chapter 13 LCD Driver (LCD) Frame frequency 85.3 Hz COM1 series: OFF COM2 series: OFF COM3 series: OFF COM1 series: ON COM2 series: OFF COM3 series: OFF COM1 series: OFF COM2 series: ON COM3 series: OFF COM1 series: ON...

  • Page 200: Chapter 14. Battery Low Detect Circuit (Bld)

    Chapter 14 Battery Low Detect Circuit (BLD)

  • Page 201: Overview

    ML63611 User’s Manual Chapter 14 Battery Low Detect Circuit (BLD) 14. Battery Low Detect Circuit (BLD) 14.1 Overview The OPTION C and OPTION D have an internal battery low detect circuit (BLD). The battery low detect circuit detects when the battery voltage (supply voltage V ) falls below the judgment voltage value.

  • Page 202: Judgment Voltage

    ML63611 User’s Manual Chapter 14 Battery Low Detect Circuit (BLD) 14.3 Judgment Voltage The value of the judgment voltage is selected by the software by setting the LD1 (bit 1 of BLDCON) and LD0 (bit 0 of BLDCON) bits. Table 14-1 lists judgment voltage and precision values.

  • Page 203: Battery Low Detect Circuit Operation

    ML63611 User’s Manual Chapter 14 Battery Low Detect Circuit (BLD) 14.5 Battery Low Detect Circuit Operation The battery low circuit is turned ON or OFF by ENBL (bit 2 of BLDCON), and outputs to BLDF (bit 3 of BLDCON) the result of a comparison with the judgment voltage.

  • Page 204: Chapter 15. Power Supply Circuit (Power)

    Chapter 15 Power Supply Circuit (POWER)

  • Page 205: Overview

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15. Power Supply Circuit (POWER) 15.1 Overview In the different voltage regulator circuits of the OPTION C and OPTION D, the battery voltage (V is halved to generate the voltage V , which is then used to generate internally the different driving voltages.

  • Page 206: Power Supply Circuit Related Register

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.2 Power Supply Circuit Related Register The halver control register (VHCON) is used to control the power supply circuit. • Halver control register (VHCON) VHCON is a 4-bit special function register (SFR) that specifies whether the output voltage of the halver circuit is used or whether the battery voltage is used as the voltage supplied to the internal different voltage regulator circuits.

  • Page 207: Power Supply Circuit Configuration

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3 Power Supply Circuit Configuration 15.3.1 OPTION A Power Supply Circuit Configuration The power supply section of the OPTION A consists of the voltage regulator circuit (V/R1) for internal logic power supply and the voltage regulator circuit (V/R2) for the low-speed clock generator circuit.

  • Page 208: Operation Of The Option A Power Supply Circuit

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3.2 Operation of the OPTION A Power Supply Circuit The battery voltage (V ) is supplied to the different voltage regulator circuits (V/R1 and V/R2) of the OPTION A. The output voltages of the voltage regulator circuits are used as the internal logic power supply (V...

  • Page 209: Option B Power Supply Circuit Configuration

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3.3 OPTION B Power Supply Circuit Configuration The power supply section of the OPTION B consists of the voltage regulator circuit (V/R1) for internal logic power supply, the voltage regulator circuit (V/R2) for the power supply of the low-speed clock generator circuit, and the voltage regulator circuit (V/R3) for the LCD bias generation reference voltage.

  • Page 210: Operation Of The Option B Power Supply Circuit

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3.4 Operation of the OPTION B Power Supply Circuit The battery voltage (V ) is supplied to the different voltage regulator circuits (V/R1, V/R2, and V/R3) of the OPTION B. The output voltages of the voltage regulator circuits are used as the internal logic power supply...

  • Page 211: Option C Power Supply Circuit Configuration

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3.5 OPTION C Power Supply Circuit Configuration The power supply section of the OPTION C consists of the halver circuit, the voltage regulator circuit (V/R1) for internal logic power supply and the voltage regulator circuit (V/R2) for the power supply of the low-speed clock generator circuit.

  • Page 212: Operation Of The Option C Power Supply Circuit

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3.6 Operation of the OPTION C Power Supply Circuit The output voltage (1/2 V ) of the halver circuit is supplied to the different voltage regulator circuits (V/R1 and V/R2) of the OPTION C. The output voltages of the voltage regulator circuits are used as the internal logic...

  • Page 213: Option D Power Supply Circuit Configuration

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3.7 OPTION D Power Supply Circuit Configuration The power supply section of the OPTION D consists of the halver circuit, the voltage regulator circuit (V/R1) for internal logic power supply, the voltage regulator circuit (V/R2) for the power supply of the low-speed clock generator circuit, and the voltage regulator circuit (V/R3) for the LCD bias generation reference voltage.

  • Page 214: Operation Of The Option D Power Supply Circuit

    ML63611 User’s Manual Chapter 15 Power Supply Circuit (POWER) 15.3.8 Operation of the OPTION D Power Supply Circuit The output voltage (1/2 V ) of the halver circuit is supplied to the different voltage regulator circuits (V/R1, V/R2, and V/R3) of the OPTION D. The output voltages of the voltage regulator circuits are used as the internal...
  • Page 215 Chapter 16 A/D Converter (ADC)

  • Page 216: Chapter 16. A/D Converter (Adc) 16.1 Overview

    16.1 Overview The ML63611 has a built-in 2-channel RC oscillation method A/D converter. The A/D converter is composed of a 2-channel oscillation circuit, Counter A (CNTA0 to 4) which is a 4.8-digit decade counter, Counter B (CNTB0 to 3) which is a 14-bit binary counter and A/D converter control registers 0 and 1 (ADCON0, ADCON1).

  • Page 217: A/D Converter Configuration

    ML63611 User’s Manual Chapter 16 A/D Converter (ADC) 16.2 A/D Converter Configuration Figure 16-1 shows the A/D converter configuration. <CNTB> 14-stage binary counter OSCCLK OVFB Differ- entiation a0-3 a4-7 a8-11 a12-13 <CNTA> 4.8-digit decade counter Interrupt request System clock (CLK)

  • Page 218: Operation Of A/D Converter

    ML63611 User’s Manual Chapter 16 A/D Converter (ADC) 16.3 Operation of A/D Converter As shown in Figure 16-1, the RC oscillation circuit can be made by connecting resistors and capacitors to each pin. × 8)) to count the system clock (CLK) which is the Counter A (CNTA0 to 4) is a 4.8-digit decade counter (1/(10...

  • Page 219: Rc Oscillation Circuit

    ML63611 User’s Manual Chapter 16 A/D Converter (ADC) 16.3.1 RC Oscillation Circuit The A/D converter of the RC oscillation method performs A/D conversion by digitizing the oscillation frequency ratio of a reference resistance (or capacitance) to a resistance sensor, such as thermistor sensor (or capacitance sensor).
  • Page 220 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) Modes No.0 and No.7 in Table 16-1 measure the external clock which is input to the IN0 pin or the IN1 pin by halting the operation of the RC oscillation circuit. As shown in Table 16-1, no two oscillation circuits can operate simultaneously. This prevents interference to the oscillation operation when two are operated simultaneously.
  • Page 221 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) Oscillation mode Oscillation with reference resistance RS0 and CS0 Oscillation with sensor RT0 and CS0 Figure 16-2 Measurement of CROSC0 by a Resistance Sensor Oscillation mode Oscillation with reference resistance RS0 and CS0...

  • Page 222: Counter A/B Reference Mode

    ML63611 User’s Manual Chapter 16 A/D Converter (ADC) 16.3.2 Counter A/B Reference Mode The conversion operation of the A/D converter is performed by one of the following two modes. • Counter A Reference Mode (SADI bit of ADCON0 = 0) This is the mode to set gate time by the system clock (CLK) and Counter A, to count the RC oscillation clock (OSCCLK) by Counter B with the gate time and to output contents of Counter B as a digital value.
  • Page 223 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) where t is the period of CLK and t is the period of OSCCLK. SYSCLK OSCCLK In other words, “nB0” is directly proportional to the RC oscillation frequency (f OSCCLK EADC SYSCLK...
  • Page 224 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) (2) Operation of Counter B Reference Mode Figure 16-7 shows the operating timing of Counter B reference mode. Counter B reference mode is performed by the following procedure: (refer to Figure 16-7) Subtract “nB1”...
  • Page 225 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) EADC SYSCLK CRON Counter A 00000 00001 00002 00003 nA1 – 3 nA1 – 2 nA1 – 1 • SYSCLK OSCCLK RC oscillation circuit input waveform IN0/IN1 OSCCLK overflow Counter B (4000 – nB1)

  • Page 226: Example Of Usage Of A/D Converter

    ML63611 User’s Manual Chapter 16 A/D Converter (ADC) 16.3.3 Example of Usage of A/D Converter The method to perform A/D conversion of sensor values by using Counter A reference mode and Counter B reference mode is explained by taking temperature measurement with a thermistor as an example.
  • Page 227 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) Consequently, by performing conversion processing corresponding to the characteristics shown by Figure 16-9 to nT0, it is possible to express temperatures by digital values. The conversion method from an analog value of RT0 to a digital value of nT0 is now explained.
  • Page 228 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) Figure 16-14 shows the timing chart for one cycle of conversion to digital values from the RT0 values, i.e. one cycle of A/D conversion. One cycle of A/D conversion needs to be composed of two steps shown in Figure 16-14 because the reference resistance and the thermistor must be oscillated independently when taking the ratio of them.
  • Page 229 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) <First step> <Second step> System 700 kHz 32.768 kHz clock (CLK) ADCON1 (Bits 2 to 0) 4H (STV = 1) 5H (STV = 1, SADI = 0, EADC = 1) 7H (STV = 1, SADI = 1, EADC = 1)
  • Page 230 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) <First Step> Set the system clock to 32.768 kHz (write 0H to FCON), if using High-speed clock as system clock. Set “80,000 – nA0” to Counter A. Note: nA0 is taken as 12,000 in order to set the gate time nA0 of oscillation mode of the reference resistance •...
  • Page 231 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) Write “7H” to ADCON0 and start A/D conversion in Counter B reference mode. Note: Since the setting of STV = 1 has already been made in the preprocessing, there is no need to wait for 120 µs.

  • Page 232: Rc Oscillation Monitor

    ML63611 User’s Manual Chapter 16 A/D Converter (ADC) 16.3.4 RC Oscillation Monitor By setting Bit 0 (MON) of the Port E mode register (PEMOD) to “1”, the RC oscillation clock (OSCCLK) can be output to PE.0. The RC oscillation monitor is useful when checking the characteristics of the RC oscillation circuit. For instance, it is possible to measure the relationship between sensors such as a thermistor and an oscillation frequency.

  • Page 233: Registers Related To A/D Converter

    ML63611 User’s Manual Chapter 16 A/D Converter (ADC) 16.4 Registers Related to A/D Converter (1) A/D converter control register 0 (ADCON0) The A/D converter control register 0 (ADCON0) is a 4-bit special function register (SFR) that selects start/stop of RC oscillation of the A/D converter and the A/D converter interrupt by Counter A or Counter B.
  • Page 234 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) (2) A/D converter control register 1 (ADCON1) The A/D converter control register 1 (ADCON1) is a 4-bit special function register (SFR) to select oscillation mode of the RC oscillation circuit. bit 3...
  • Page 235 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) (3) A/D converter counter A registers (CNTA0 to 4) The A/D converter counter A registers (CNTA0 to 4) are 4-bit special function registers (SFRs) to read/write the Counter A. Note: CNTA0 to CNTA3 are decimal counters and can handle only data from 0H to 9H.
  • Page 236 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) (4) A/D converter counter B registers (CNTB0 to 3) The A/D converter counter B registers (CNTB0 to 3) are 4-bit special function registers (SFRs) to read/write the Counter B. bit 3 bit 2...
  • Page 237 ML63611 User’s Manual Chapter 16 A/D Converter (ADC) Tables 16-3 and 16-4 list A/D converter-related registers and pins. Table 16-3 List of A/D Converter-Related Registers Register name Symbol Address Read/Write Value at system reset A/D converter control register 0 ADCON0...

  • Page 238: Appendixes

    Appendixes...

  • Page 239: Appendix A List Of Special Function Registers

    ML63611 User’s Manual Appendix A Appendix A List of Special Function Registers The Special Function Registers of the ML63611 are listed in Table A. “—” indicates an invalid bit. Table A Special Function Register List Initial value Register name Symbol...
  • Page 240 ML63611 User’s Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address bit 3 bit 2 bit 1 bit 0 at system reset 039H Reserved 03CH Port E control register 0 PECON0 03DH PE1MD1 PE1MD0 PE0MD1 PE0MD0...
  • Page 241 ML63611 User’s Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address bit 3 bit 2 bit 1 bit 0 at system reset Timer 0 counter register L TM0CL 06CH T0C3 T0C2 T0C1 T0C0...
  • Page 242 ML63611 User’s Manual Appendix A Table A Special Function Register List (continued) Initial value Register name Symbol Address bit 3 bit 2 bit 1 bit 0 at system reset Serial port send buffer L STBUFL 0A4H Serial port send buffer H...

  • Page 243: Appendix B Input/Output Circuit Configuration

    ML63611 User’s Manual Appendix B Appendix B Input/Output Circuit Configuration (1) I/O Port (PA.0–PA.3, PB.0–PB.3, PC.0–PC.3, PE.0–PE.3) Pull-up/pull-down control Gate control circuit Output data Output control Input data Schmitt trigger input inside the IC (2) Input Port (P0.0–P0.3) Pull-up/pull-down control...
  • Page 244 ML63611 User’s Manual Appendix B (3) Low-Speed Oscillation Circuit Time base clock CMOS input (TBCCLK) inside the IC (4) High-Speed Oscillation Circuit Oscillation start High-speed clock OSC0 CMOS input (HSCLK) OSC1 inside the IC (5) RESET, TST1, and TST2 Inputs...

  • Page 245: Appendix C Peripheral Circuit Examples

    ML63611 User’s Manual Appendix C Appendix C Peripheral Circuit Examples 1.5 V L0–L31 L36–L63 0.1 µF OSC0 Ceramic resonator 15 pF OSC1 Crystal L32 (LP0.3) Open L33 (LP0.2) L34 (LP0.1) Open L35 (LP0.0) Open P0.3 1.0 µF P0.2 P0.1 1.0 µF P0.0...
  • Page 246 ML63611 User’s Manual Appendix C 1.5 V L0–L63 0.1 µF OSC0 15 pF OSC1 Crystal Open Open P0.3 P0.2 Open P0.1 1.0 µF P0.0 1.0 µF PB.3 ML63611 1.0 µF PB.2 PB.1 (OPTION B) PB.0 1.0 µF PA.3 0.1 µF PA.2...
  • Page 247 ML63611 User’s Manual Appendix C L0–L31 L36–L63 0.1 µF OSC0 Ceramic resonator 15 pF OSC1 Crystal L32 (LP0.3) L33 (LP0.2) 0.1 µF L34 (LP0.1) L35 (LP0.0) 0.1 µF P0.3 1.0 µF P0.2 P0.1 P0.0 1.0 µF ML63611 PB.3 (OPTION C) PB.2...
  • Page 248 ML63611 User’s Manual Appendix C L0–L63 0.1 µF OSC0 Ceramic resonator 15 pF OSC1 Crystal 0.1 µF P0.3 0.1 µF P0.2 P0.1 1.0 µF P0.0 1.0 µF PB.3 1.0 µF ML63611 PB.2 (OPTION D) PB.1 PB.0 1.0 µF PA.3 0.1 µF PA.2...

  • Page 249: Appendix D Instruction List

    ML63611 User’s Manual Appendix D Appendix D Instruction List The format used in the list of instructions is indicated below. INSTRUCTION CODE FLAG MNEMONIC OPERATION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G Flags marked with (√)
  • Page 250 ML63611 User’s Manual Appendix D Transfer Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 direct ← A MOV direct,A — — — [HL] ← A MOV [HL],A 0 —...
  • Page 251 ML63611 User’s Manual Appendix D Rotate Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 C ← { } ← C, A ← sfr √...
  • Page 252 ML63611 User’s Manual Appendix D Increment/Decrement Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 sfr,A ← sfr + 1 √ √ — INC sfr cur,A ←...
  • Page 253 ML63611 User’s Manual Appendix D Arithmetic Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 sfr,A ← sfr + A √ √ — ADD sfr,A cur,A ←...
  • Page 254 ML63611 User’s Manual Appendix D Arithmetic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 sfr,A ← decimal adjustment √ √ — ADCD sfr,A {sfr + A + C} cur,A ←...
  • Page 255 ML63611 User’s Manual Appendix D Arithmetic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 sfr,A ← sfr – A √ √ —...
  • Page 256 ML63611 User’s Manual Appendix D Arithmetic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 sfr,A ← decimal adjustment √ √ — SBCD sfr,A {sfr –...
  • Page 257 ML63611 User’s Manual Appendix D Compare Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 √ √ — CMP sfr,A sfr – A √...
  • Page 258 ML63611 User’s Manual Appendix D Logic Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 sfr,A ← sfr ∧ A √ — — AND sfr,A cur,A ←...
  • Page 259 ML63611 User’s Manual Appendix D Logic Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 cur,A ← cur ∨ i4 √ — —...
  • Page 260 ML63611 User’s Manual Appendix D Mask Operation Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 Testing of all bits in sfr not √ — —...
  • Page 261 ML63611 User’s Manual Appendix D Mask Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 Clearing of all bits in cur not √...
  • Page 262 ML63611 User’s Manual Appendix D Mask Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 Setting of all bits in cur not √...
  • Page 263 ML63611 User’s Manual Appendix D Mask Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 Inverting of all bits in cur not √...
  • Page 264 ML63611 User’s Manual Appendix D Bit Operation Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 √ — — BTST \cur.n Bit testing of cur.n √...
  • Page 265 ML63611 User’s Manual Appendix D Bit Operation Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 cur.n ← cur.n, A ← cur √ — —...
  • Page 266 ML63611 User’s Manual Appendix D ROM Table Reference Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 [HL],[HL + 1] ← (RA) MOVHB [HL],[RA] 0 —...
  • Page 267 ML63611 User’s Manual Appendix D ROM Table Reference Instructions (continued) INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 [HL],[HL + 1] ← (RA) MOVLB [HL],[RA] 1 —...
  • Page 268 ML63611 User’s Manual Appendix D Stack Operation Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 (RSP) ← {FLAG, A, HL}, PUSH HL 0 — — —...
  • Page 269 ML63611 User’s Manual Appendix D Conditional Branch Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 BC radr8 if C = 1 then — — —...
  • Page 270 ML63611 User’s Manual Appendix D Control Instructions INSTRUCTION CODE FLAG MNEMONIC OPERATION 9 8 7 6 5 4 3 2 1 0 Z C G 15 14 13 12 11 10 NO OPERATION 0 — — — HALT HALT CPU 1 —...
  • Page 271 ML63611 User’s Manual First Edition: May 2001 Second Edition: June 2001     2001 Oki Electric Industry Co., Ltd. PEUL63611-02...

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