Port B External Interrupt Function (External Interrupt 0) - Oki ML63611 User Manual

10.5.3 Port B External Interrupt Function (External Interrupt 0)

Port B has external interrupt 0 allocated as secondary function. Individual bits can be enabled/disabled for
external interrupt 0.
External interrupt generation for port B is triggered by the falling edge of the 128 Hz or 4 kHz time base counter,
which is the sampling clock.
After the port level changes, the interrupt request signal (XI0INT) is output, and the interrupt request flag (QXI0)
is set. The maximum delay for this sequence is one cycle of the sampling clock (128 Hz or 4 kHz).
Because the port B external interrupt is set by a level change at any of the port B inputs, each bit of the port must
be read to determine which bit of port B generated the interrupt.
The interrupt start address for external interrupt 0 is 0014H.
Figure 10-8 shows the equivalent circuit for external interrupt 0 control.
PBCON0, PBCON1
PB.0
PB0MD1
PB.1
PB1MD1
PB.2
PB2MD1
PB.3
PB3MD1
Figure 10-8 External Interrupt 0 Control Equivalent Circuit
Figure 10-9 shows the external interrupt 0 generation timing.
(a) PB0MD1 to PB3MD1 = "0" (initial value: inputs with pull-down resistors or high impedance input)
setting
• When all PB.0 to PB.3 inputs are at a "L" level
External interrupt 0 is generated when any port B input changes to a "H" level.
• When any of PB.0 to PB.3 inputs is at a "H" level
External interrupt 0 is generated when all the port B inputs change to a "L" level.
(b) PB0MD1 and PB1MD1 = "0" and PB2MD1 and PB3MD1 = "1" (PB.0 and PB.1 selected as inputs with
pull-down resistors or high impedance input; PB.2 and PB.3 selected as inputs with pull-up resistors or
high impedance input) setting
• When both PB.0 and PB.1 inputs are at a "L" level AND both PB.2 and PB.3 inputs are at a "H"
level
External interrupt 0 is generated when either PB.0 or PB.1 input changes to a "H" level
(alternatively, when either PB.2 or PB.3 input changes to a "L" level).
• When either PB.0 or PB.1 input is at a "H" level OR either PB.2 or PB.3 input is at a "L" level
External interrupt 0 is generated when both PB.0 and PB.1 inputs change to a "L" level AND both
PB.2 and PB.3 inputs change to a "H" level.
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
PBIE
PB0IE
PB1IE
PB2IE
PB3IE
128 Hz
4 kHz
PBMOD
PBF
10 – 17
Chapter 10 Ports (INPUT, I/O PORT)
IRQ0
IRQ0.2
Level change
XI0INT
detect circuit
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
IE0
to interrupt priority
IE0.2
encoder
EXI0
QXI0
circuit for LCD bias