Port 0 External Interrupt Function (External Interrupt 5) - Oki ML63611 User Manual

10.3.3 Port 0 External Interrupt Function (External Interrupt 5)

Port 0 has external interrupt 5 allocated as secondary function. Individual bits can be enabled/disabled for external
interrupt 5.
External interrupt generation for each input of port 0 is triggered by the falling edge of either the 128 Hz or 4 kHz
sampling clock from the time base counter.
After the port level changes, interrupt request signal XI5INT is output and external interrupt 5 request flag (QXI5)
is set. The maximum time delay from the change in port level until setting QXI5 is one cycle of the sampling
clock (128 Hz or 4 kHZ).
Because the port 0 external interrupt 5 is set by a level change at any of the port 0 inputs, each bit of the port must
be read to determine which bit of port 0 generated the interrupt.
The interrupt vector address for external interrupt 5 is 001EH.
Figure 10-2 shows an equivalent circuit of external interrupt 5 control.
P0.0
P0.1
P0.2
P0.3
Figure 10-2 Equivalent Circuit of External Interrupt 5 Control
Figure 10-3 shows the timing for generation of external interrupt 5.
(a) P0PUD = "0" (initial value: inputs with pull-down resistors) setting
• When all P0.0 to P0.3 inputs are at a "L" level
External interrupt 5 is generated when any port 0 input changes to a "H" level.
• When any of P0.0 to P0.3 inputs is at a "H" level
External interrupt 5 is generated when all the port 0 inputs change to a "L" level.
(b) P0PUD = "1" (inputs with pull-up resistors) setting
• When all P0.0 to P0.3 inputs are at a "H" level
External interrupt 5 is generated when any port 0 input changes to a "L" level.
• When any of P0.0 to P0.3 inputs is at a "L" level
External interrupt 5 is generated when all the port 0 inputs change to a "H" level.
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
P0IE
P00IE
P01IE
Level change
detection circuit
P02IE
P03IE
128 Hz
4 kHz
Sampling signal
P0CON1
P0PUD
P0F
Chapter 10 Ports (INPUT, I/O PORT)
IRQ1
IRQ1.3
QXI5
XI5INT
10 – 5
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
To interrupt
priority encoder
IE1
circuit
IE1.3
EXI5
circuit for LCD bias