Port B Registers - Oki ML63611 User Manual

ML63611 User's Manual
Chapter 10 Ports (INPUT, I/O PORT)

10.5.2 Port B Registers

The following registers are used to control port B:
(1) Port B data register (PBD)
(2) Port B direction register (PBDIR)
(3) Port B control registers 0/1 (PBCON0, PBCON1)
(4) Port B mode register (PBMOD)
(5) Port B interrupt enable register (PBIE)
(1) Port B data register (PBD)
PBD is a 4-bit special function register used to set the output values for port B.
When a bit in the port B direction register (PBDIR) is set to "1" to select the output mode, the content of the
corresponding bit in the port B data register is output to the port B.
When a bit in the port B data register is read with the corresponding PBDIR bit set to output, the value of the
bit in the port B data register is read.
When a bit in the port B data register is read with the corresponding PBDIR bit set to "0" (input mode), the
level of the corresponding pin of port B is read.
PBD (00BH)
Port B output data
At system reset all bits in the port B data register (PBD) are set to "0". When data is written to the port B
data register, the actual pin change timing is at the rising edge of the system clock for state 2 of the write
instruction.
Figure 10-7 indicates port B change timing.
CLK
Port B
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
bit 3
PB3
(R/W)
Write instruction
S1
Old data
Figure 10-7 Port B Change Timing
10 – 12
bit 2 bit 1
PB2 PB1
S2
New data
OPTION B (D): 1.5 V (3.0 V), With regulator
bit 0
PB0
circuit for LCD bias