Overview; Watchdog Timer Configuration - Oki ML63611 User Manual

9. Watchdog Timer (WDT)
9.1

Overview

The watchdog timer is a circuit to detect CPU malfunction. The WDT consists of a 9-bit watchdog timer counter
(WTDC) counting the 256 Hz output of the TBC7 of the time base counter (TBC), and a watchdog timer control
register (WDTCON) to start and clear WDTC.
9.2

Watchdog Timer Configuration

Figure 9-1 shows the configuration of the watchdog timer.
Internal pointer
T
WDTCON
WRITE
Data bus
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
Q
R
4
"5H" detection
and latch
4
"0AH" detection
256 Hz
(from time base counter)
Figure 9-1 Watchdog Timer Configuration
Chapter 9 Watchdog Timer (WDT)
WDTCON
R
9
1/2
WDTC
Watchdog timer counter
9 – 1
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
QWDACK
(internal reception signal)
RESETS
(system reset)
WDTINT
(interrupt request)
circuit for LCD bias