Table of Contents
Advertisement
4.2
Interrupt Registers
The following three types of registers are used to control interrupts.
(1) Master interrupt enable register (MIEF)
(2) Interrupt enable registers (IE0 to IE4)
(3) Interrupt request registers (IRQ0 to IRQ4)
These registers are described below.
(1) Master interrupt enable register (MIEF)
MIEF is a 4-bit register in which bit 0 is the master interrupt enable flag (MIE).
MIE (bit 0 of MIEF) is a flag that disables or enables all interrupts except for the watchdog timer interrupt.
If MIE is "0", all interrupts are disabled. If MIE is "1", all interrupts are enabled (with the exception of the
watchdog timer).
When any interrupt is received, MIE is cleared to "0". MIE is set to "1" by execution of a return from
interrupt instruction (RTI instruction).
If multi-level interrupt processing is to be performed, execute an RTI instruction (MIE←"1") during the
interrupt processing routines.
At system reset, MIE is initialized to "0". MIEF only supports data reference (R) of data memory through
addressing instructions.
Master Interrupt Enable Flag
0: Interrupts disabled (initial value)
1: Interrupts enabled
!
Note:
When setting MIE, use "EI" instructions (MIE←"1") and "DI" instructions (MIE←"0").
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
bit 3
MIEF
(0FFH)
(R)
4 – 3
ML63611 User's Manual
Chapter 4 Interrupt (INT)
bit 2
bit 1
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
bit 0
MIE
Advertisement
Table of Contents
