System Clock Select Timing - Oki ML63611 User Manual

5.7

System Clock Select Timing

After system reset, the system clock is TBCCLK.
When high-speed operation is necessary, switch the system clock to HSCLK.
A flowchart of system clock operation is shown below.
Software processing
(2) High-speed clock oscillation stop
ENOSC (bit 1 of FCON) = "0"
ENOSC = "0" : Stop high-speed clock oscillation
(initial value)
ENOSC = "1" : Start high-speed clock oscillation
(1) Low-speed clock oscillation output select
CPUCLK (bit 0 of FCON) = "0"
CPUCLK = "0" : Low-speed clock oscillation output
(initial value)
CPUCLK = "1" : High-speed clock oscillation output
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
System clock status
TBCCLK
(Low-speed clock generator circuit output)
HSCLK
(High-speed clock generator circuit output)
5 – 7
Chapter 5 Clock Generator Circuit (OSC)
After system reset, the low-
speed clock generator output
is the system clock.
Software processing
(1) High-speed clock oscillation mode select
OSCSEL (bit 2 of FCON) setting
OSCSEL = "0" : RC oscillation mode
(initial value)
OSCSEL = "1" : Ceramic oscillation mode
(2) High-speed clock oscillation start
ENOSC (bit 1 of FCON) = "1"
ENOSC = "0" : Stop high-speed clock oscillation
(initial value)
ENOSC = "1" : Start high-speed clock oscillation
Wait:
When RC oscillation mode selected:
300 µs or more
When ceramic oscillation mode selected:
10 ms or more
(3) High-speed clock oscillation output select
CPUCLK (bit 0 of FCON) = "1"
CPUCLK = "0" : Low-speed clock oscillation output
(initial value)
CPUCLK = "1" : High-speed clock oscillation output
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
circuit for LCD bias