Watchdog Timer Control Register (Wdtcon); Watchdog Timer Operation - Oki ML63611 User Manual

ML63611 User's Manual
Chapter 9 Watchdog Timer (WDT)
9.3

Watchdog Timer Control Register (WDTCON)

The watchdog timer control register (WDTCON) is a 4-bit write-only special function register (SFR) used to
start/clear the watchdog timer counter (WDTC).
WDTCON (09FH)
(W)
9.4

Watchdog Timer Operation

At system reset, WDTC (watchdog timer counter) stops counting.
WDTC begins counting by writing "5H" to WDTCON (watchdog timer control register) while the internal pointer
is "0", and then writing "0AH" (while the internal pointer is "1").
The internal pointer is cleared to "0" at system reset or when WDTC overflows, and toggles every time a write
operation to WDTCON is performed.
After WDTC is activated, WDTC is cleared by writing "5H" to WDTCON while the internal pointer is "0", and
then writing "0AH" while the internal pointer is "1". When WDTC overflows (1FFH→000H), a watchdog timer
interrupt request (WDTINT) is generated. WDTINT cannot be disabled by the software (non-maskable interrupt)
and has the highest level of interrupt priority.
The WDTC overflow cycle (T) is given by:
128 × 512
T =
32768 (Hz)
The minus deviation (t) of the WDTC overflow cycle is given by:
128
t =
32768 (Hz)
Therefore, the WDTC clear cycle (Ct) can be computed as follows.
Ct = T – t = 2 s – 3.9 ms = 1.9961 s
If 32.768 kHz is to be used as the low-speed clock, the software must be programmed to clear WDTC within
1.9961 s.
If the CPU malfunctions due to a power failure or other factor and the WDTC cannot be cleared normally, WDTC
will overflow and WDTINT will be generated. Program the watchdog timer interrupt routine to handle recovery
operations by returning to the normal routine.
!
Note:
The watchdog timer cannot detect all operating faults. If the CPU malfunctions but WDTC can still be cleared, a fault
will not be detected.
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
bit 3
d3
= 2 s
= approximately 3.9 ms
bit 2 bit 1
d2 d1
9 – 2
OPTION B (D): 1.5 V (3.0 V), With regulator
bit 0
d0
circuit for LCD bias