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15.3.5 OPTION C Power Supply Circuit Configuration
The power supply section of the OPTION C consists of the halver circuit, the voltage regulator circuit (V/R1) for
internal logic power supply and the voltage regulator circuit (V/R2) for the power supply of the low-speed clock
generator circuit.
The OPTION C does not have the voltage regulator circuit (V/R3) for the LCD bias generation reference voltage.
Since the power supply voltage is used as the LCD bias generation reference voltage, the pin V
shorted to V
.
DD
The OPTION C power supply circuit configuration is shown in Figure 15-3.
Software selection
During normal load
(when V
VH (bit 0 of VHCON) = "1"
V/R2
0.7 V
V/R1
1.15 V
ENOSC (bit 1 of FCON) = "1"
Figure 15-3 OPTION C Power Supply Circuit Configuration
!
Note:
When operating with the high-speed clock, first set VH (bit 0 of VHCON) to "0" and then set ENOSC (bit 1 of
FCON) to "1".
If VH is the "1" state, the halver circuit output voltage (V
circuits and the operation will not be made properly.
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
During heavy load
(when V
= 1.8 to 2.4 V)
DD
VH (bit 0 of VHCON) = "0"
V
HF
1/2V
= 2.4 to 3.6 V)
DD
V
XT
ENOSC (bit 1 of FCON) = "0"
V
CH
Internal logic circuits (ROM, RAM, CPU, etc.)
High-speed clock generator circuit
Chapter 15 Power Supply Circuit (POWER)
1.8 to 3.6 V
Halver circuit
DD
LCD bias circuit
Low-speed clock
generator circuit
ML63611
) becomes the power supply (V
HF
15 – 7
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
DD2
V
3.0 V
DD
C
0.1 µF
V
0.1 µF
V
C
HF
HF
HC2
0.1 µF
C
HC1
H12
V
1.0 µF
C
DD3
3
V
DD2
1.0 µF
V
C
DD1
1
C2
1.0 µF
C
C1
12
XT0
C
G
5 to 25 pF
XT1
32.768 kHz
0.1 µF
V
C
XT
XT
0.1 µF
V
C
CH
CH
30 pF
C
OSC0
L0
C
OSC1
L1
V
Ceramic resonator
SS
) for the internal logic
CH
circuit for LCD bias
has to be
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