Port C External Interrupt Function (External Interrupt 1) - Oki ML63611 User Manual

10.6.3 Port C External Interrupt Function (External Interrupt 1)

Port C has external interrupt 1 allocated as secondary function. Individual bits can be enabled/disabled for
external interrupt 1.
External interrupt generation for port C is triggered by the falling edge of the 128 Hz or 4 kHz time base counter,
which is the sampling clock.
After the port level changes, the interrupt request signal (XI1INT) is output, and the interrupt request flag (QXI1)
is set. The maximum delay for this sequence is one cycle of the sampling clock (128 Hz or 4 kHz).
Because the port C external interrupt 1 is set by a level change at any of the port C inputs, each bit of the port
must be read to determine which bit of port C generated the interrupt.
The interrupt start address for external interrupt 1 is 0016H.
Figure 10-12 shows the equivalent circuit for external interrupt 1 control.
PCCON0, PCCON1
PC.0
PC0MD1
PC.1
PC1MD1
PC.2
PC2MD1
PC.3
PC3MD1
Figure 10-12 External Interrupt 1 Control Equivalent Circuit
Figure 10-13 shows the external interrupt 1 generation timing.
(a) PC0MD1 to PC3MD1 = "0" (initial value: inputs with pull-down resistors or high impedance input)
setting
• When all PC.0 to PC.3 inputs are at a "L" level
External interrupt 1 is generated when any port C input changes to a "H" level.
• When any of PC.0 to PC.3 inputs is at a "H" level
External interrupt 1 is generated when all the port B inputs change to a "L" level.
(b) PC0MD1 and PC1MD1 = "0" and PC2MD1 and PC3MD1 = "1" (PC.0 and PC.1 selected as inputs with
pull-down resistors or high impedance input; PC.2 and PC.3 selected as inputs with pull-up resistors or
high impedance input) setting
• When both PC.0 and PC.1 inputs are at a "L" level AND both PC.2 and PC.3 inputs are at a "H"
level
External interrupt 1 is generated when either PC.0 or PC.1 input changes to a "H" level
(alternatively, when either PC.2 or PC.3 input changes to a "L" level).
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
PCIE
PC0IE
PC1IE
PC2IE
PC3IE
128 Hz
4 kHz
PCMOD
PCF
10 – 25
Chapter 10 Ports (INPUT, I/O PORT)
IRQ0
IRQ0.3
Level change
XI1INT
detect circuit
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
IE0
to interrupt priority
IE0.3
encoder
EXI1
QXI1
circuit for LCD bias