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8. 100 Hz Timer Counter (100HzTC)
8.1
Overview
The 100 Hz timer counter has a circuit that divides the TBC6 output (512 Hz) of the time base counter to generate
a 10 Hz interrupt. The 100 Hz timer consists of a 5/6-base counter and two decimal counters.
8.2
100 Hz Timer Counter Configuration
Figure 8-1 indicates the configuration of the 100 Hz timer counter.
512 Hz
ECNT
T10CR WRITE
T100CR WRITE
T10CR READ
T100CR READ
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
Decimal counter
5/6-base counter
R
R
L
Figure 8-1 100 Hz Timer Counter Configuration
Chapter 8 100 Hz Timer Counter (100HzTC)
T100CR
T10CR
Decimal counter
R
4-bit latch
8 – 1
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
T10HzINT
bit 3
bit 2
bit 1
Data
bit 0
bus
bit 3
bit 2
bit 1
bit 0
circuit for LCD bias
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