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5. Clock Generator Circuit (OSC)
5.1
Overview
The ML63611 has built in it a low-speed clock generator circuit and a high-speed clock generator circuit, and the
system clock that becomes the basic operating clock of the CPU section is controlled using the frequency control
register (FCON).
The low-speed clock generator circuit is configured using a crystal oscillator circuit. A crystal unit (32.768 kHz) is
connected between the pins XT0 and XT1, and a capacitor (5 to 25 pF) is connected between the pins XT0 and
V
. The output (TBCCLK) of the low-speed clock generator circuit becomes the basic operating clock for the
SS
time base counter etc., and is used as the system clock.
In the high-speed clock generator circuit, it is possible to select by software either the ceramic oscillation mode or
the RC oscillation mode. In the OPTION A and OPTION B, however, only the RC oscillation mode is available.
For the ceramic oscillator mode, connect a ceramic unit (700 kHz max.) between the pins OSC0 and OSC1, and
connect a capacitor C
When not using the high-speed clock generator circuit, leave the pins OSC0 and OSC1 open. It is possible to
select the output (HSCLK) of the high-speed clock generator circuit as the clock for the timer etc., and will be
used as the system clock.
The frequency control register (FCON) is a 4-bit special function register that selects the system clock (TBCCLK
or HSCLK) and the starting and stopping of the operation of the high-speed clock generator circuit.
During a system reset, the operation is made only of the low-speed clock generator circuit (the high-speed clock
generator circuit will be in the halted state), and TBCCLK will be selected as the system clock.
5.2
Clock Generator Circuit Configuration
Figure 5-1 shows a block diagram of the clock generator circuit.
XT0
XT1
Low-speed clock generator circuit
OSC1
OSC0
High-speed clock generator circuit
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
between the pins OSC0 and V
L0
V
DDL
Low-speed clock output
V
DDH
High-speed clock output
RC/ceramic oscillation select
Oscillation enable
FCON WRITE
Figure 5-1 Clock Generator Circuit Configuration
Chapter 5 Clock Generator Circuit (OSC)
and a capacitor C
SS
TBCCLK
HSCLK
Clock select
control
3
FCON
3
5 – 1
OPTION B (D): 1.5 V (3.0 V), With regulator
ML63611 User's Manual
between the pins OSC1 and V
L1
Time base clock
(TBCCLK)
System clock
(CLK)
High-speed clock
(HSCLK)
Data bus
circuit for LCD bias
.
SS
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