Page 1 FEUL66591-66592-01 MSM66591/ML66592 User's Manual CMOS 16-bit microcontroller Issue Date: Mar. 4, 2002...
Page 2 Preface This document describes the hardware of the 16-bit microcontrollers MSM66591/ML66592 that employ Oki-original CPU core nX-8/500S. Shown below are the related manuals. Refer to them as required. nX-8/500S Core Instruction Manual • Description of nX-8/500S core instruction set • Description of addressing modes MAC66K Assembler Package User’s Manual...
Page 3 Notation Classification Notation Description n Numeric value Represents a hexadecimal number Represents a binary number n Unit Word, W 1 word = 16 bits byte, B 1 byte = 2 nibbles = 8 bits nibble, N 1 nibble = 4 bits mega-, M kilo-, K = 1024...
Page 4: Table Of Contents
Contents Chapter 1 Overview Features ......................1-2 Block Diagram ....................1-4 Pin Configuration ................... 1-5 Basic Operation Timing ................. 1-6 Chapter 2 Description of Pins P0_0–P0_7: Input/Output Pins ..............2-1 P1_0–P1_7: Input/Output Pins ..............2-1 P2_0–P2_7: Input/Output Pins ..............2-1 P3_0–P3_7: Input/Output Pins ..............
Page 5 Chapter 3 CPU Architecture Memory Space ....................3-1 3.1.1 Memory Space Expansion ................3-1 3.1.2 Program Memory Space ................3-2 [1] Accessing Program Memory Space ............3-4 [2] Vector Table Area ..................3-4 [3] VCAL Table Area ..................3-6 [4] ACAL Area ....................3-7 3.1.3 Data Memory Space ...................
Page 6 3.3.2 ROM Addressing ..................3-51 [1] Immediate Addressing ................3-51 [2] Table Data Addressing ................3-51 [3] Program Code Addressing ............... 3-53 [4] ROM Window Addressing ................. 3-55 Chapter 4 CPU Control Functions Standby Function ................... 4-1 4.1.1 Standby Control Register (SBYCON) ............4-3 4.1.2 Operation in Each Standby Mode ...............
Page 7 Port 5 (P5) ....................6-19 Port 6 (P6) ....................6-21 6.10 Port 7 (P7) ....................6-23 6.11 Port 8 (P8) ....................6-25 6.12 Port 9 (P9) ....................6-27 6.13 Port 10 (P10) ....................6-29 6.14 Port 11 (P11) ....................6-31 6.15 Port 12 (P12) ....................
Page 8 11.4 Type A2 Register Modules (TMR14, TMR15) ........... 11-17 11.4.1 Configuration of Type A2 Register Modules (TMR14, TMR15) .... 11-17 [1] Timer Registers (TMR14, TMR15) ............11-17 [2] Capture Control Register (CAPCON) ............. 11-18 [3] Event Control Register 2 (EVNTCON2) ..........11-19 [4] Event Dividing Counters 14, 15 (EVDV14, EVDV15) ......
Page 9 Chapter 12 General-Purpose 8-Bit Timer Function 12.1 General-Purpose 8-Bit Timer (GTM) ............12-2 [1] General-Purpose 8-Bit Timer Counter (GTMC) ........12-3 [2] General-Purpose 8-Bit Timer Register (GTMR) ........12-3 [3] General-Purpose 8-Bit Timer Control Register (GTMCON) ..... 12-3 [4] General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) ..12-5 12.2 General-Purpose 8-Bit Event Counter (GEVC) ...........
Page 10 14.5 Configuration of SCI2 Timer (S2TM) ............14-9 [1] SCI2 Timer Counter .................. 14-9 [2] SCI2 Timer Register ................. 14-9 [3] SCI2 Timer Control Register (S2CON) ............. 14-9 14.6 Operation of SCI2 Timer ................14-11 14.7 Configuration of SCI3 Timer (S3TM) ............14-12 [1] SCI3 Timer Counter ................
Page 11 15.2.3 Control Registers for SCI2 ..............15-26 [1] SCI2 Transmit Control Register (ST2CON) ..........15-26 [2] SCI2 Receive Control Register (SR2CON) ..........15-28 [3] SCI2 Transmit/Receive Buffer Register (S2BUF0) ......... 15-30 [4] SCI2 Receive Buffer Registers (S2BUF1, S2BUF2, S2BUF3) ....15-30 [5] SCI2 Transmit and Receive Registers ............
Page 12 Chapter 16 A/D Converter Functions 16.1 Configuration of A/D Converter ..............16-4 [1] Scan Mode ....................16-4 [2] Select Mode ....................16-4 [3] Hard Select Mode ..................16-4 16.2 Control Register of A/D Converter ............... 16-7 [1] A/D Control Register 0L (ADCON0L) ............16-7 [2] A/D Control Register 1L (ADCON1L) ............
Page 13 Chapter 20 Interrupt Request Processing Function 20.1 Non-maskable Interrupt (NMI) ..............20-2 20.2 Maskable Interrupt ..................20-4 [1] Interrupt Request Flag Disable Register IRQD (IRQD0L, IRQD0H, IRQD1L, IRQD1H, IRQD2L) ......20-6 [2] Interrupt Request Register IRQ (IRQ0L, IRQ0H, IRQ1L, IRQ1H, IRQ2L) ... 20-6 [3] Interrupt Enable Register IE (IE0L, IE0H, IE1L, IE1H, IE2L) ....
Page 14 RAM Monitor Function Operation ..............24-5 [1] Setting the addresses ................24-5 [2] Detection of address matching ..............24-5 [3] Reading data .................... 24-5 Chapter 25 Electrical Characteristics [MSM66591 Electrical Characteristics] ............... 25-1 25.1 Absolute Maximum Ratings ................. 25-1 25.2 Operating Range ..................25-2 25.3 DC Characteristics ..................
Page 15 Contents-12...
Page 16 Chapter 1 Overview Chapter 2 Description of Pins Chapter 3 CPU Architecture Chapter 4 CPU Control Functions Chapter 5 Memory Control Functions Chapter 6 Port Functions Chapter 7 Output Pin Control Pin (OE) Chapter 8 Clock Generation Circuit Chapter 9 Time Base Counter (TBC) Chapter 10 Watchdog Timer (WDT)
Page 18: Chapter 1 Overview
Chapter 1 Overview...
Page 20 CPU (nX-8/500S), ROM, RAM, a 10-bit A/D converter, serial ports, flexible timers, and PWMs. The ML66592 is the same as the MSM66591 with the exception that the ML66592 has an increased ROM and RAM capacity and a higher operating speed. Table 1-1 lists the func- tional differences between the MSM66591 and ML66592.
Page 21: Features
• Page addressing • Pointing register indirect addressing • Stack addressing • Immediate addressing Minimum Instruction Cycle MSM66591: 83.3 nsec @ 12 MHz (internal: 24 MHz) ML66592: 71.4 nsec @ 14 MHz (internal: 28 MHz) Program Memory (ROM) MSM66591: Internal: 128K bytes...
Page 22 MSM66591/ML66592 User's Manual Chapter 1 Overview Flexible Timer • Freerun counter: 20-bit ¥ 1, 16-bit ¥ 1 • Capture register with divider: 6 • Double-buffer realtime output: 10 • Multifunction timer: 2 General-Purpose 8-Bit Timers • General-purpose 8-bit timer: 1 •...
Page 23: Block Diagram
MSM66591/ML66592 User's Manual Chapter 1 Overview 1.2 Block Diagram CAP0/P3_4 6K bytes 128K bytes ALE/P7_2 CAP3/P3_7 PSEN/P7_3 RTO4/P2_0 AD0/P0_0 CPU CORE Flexible RTO13/P10_1 Port Timer Cont. CAP14/P10_2 AD7/P0_7 CAP15/P10_3 Memory Cont. A8/P1_0 FTM16/P10_4 Pointing Reg. Local Reg. FTM17A/P3_0 Instruction A16/P12_0 Dec.
Page 24: Pin Configuration
MSM66591/ML66592 User's Manual Chapter 1 Overview 1.3 Pin Configuration P2_5/RTO9 P2_4/RTO8 P2_3/RTO7 P2_2/RTO6 P2_1/RTO5 P2_0/RTO4 P11_7 P11_6 P11_5 P11_4 P11_3/(RMACK) P11_2/(RMCLK) P11_1/(RMTX) P11_0/(RMRX) AI10 TEST AI11 P12_1/A17 AI12 P12_0/A16 AI13 P1_7/A15 AI14 P1_6/A14 AI15 P1_5/A13 AI16 P1_4/A12 AI17 P1_3/A11 AI18...
Page 25: Basic Operation Timing
(CLK). One master clock pulse (CLK) forms one state. In other words, one state is 41.7 nsec (@ 12 MHz) for the MSM66591 or 35.7 nsce (@ 14 MHz) for the ML66592. The execution of a single instruction is performed over several states (S2, S3, …Sn).
Page 26 MSM66591/ML66592 User's Manual Chapter 1 Overview...
Page 27 MSM66591/ML66592 User's Manual Chapter 1 Overview...
Page 28 MSM66591/ML66592 User's Manual Chapter 1 Overview...
Page 29 MSM66591/ML66592 User's Manual Chapter 1 Overview 1-10...
Page 30: Chapter 2 Description Of Pins
Chapter 2 Description of Pins...
Page 32: P0_0-P0_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins 2. Desacacription of Pins Chapter 2 describes each pin of the MSM66591/ML66592. For handling of unused pins, see Section 2.27. 2.1 P0_0–P0_7: Input/Output Pins 8-bit I/O pins of Port 0. I/O can be specified in bit units by the Port 0 mode register (P0IO).
Page 33: P3_0-P3_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins For the pins that have secondary functions set by P2SF, I/O settings by P2IO become invalid. <Description of the Secondary Functions of Each Pin> • RTO4 (P2_0)–RTO11 (P2_7) The preset level is output when the value of registers 4–11 (TMR4–TMR11) of the flexible timer match the selected counter values.
Page 34: P4_0-P4_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins 2.5 P4_0–P4_7: Input/Output Pins 8-bit I/O pins of Port 4. I/O can be specified in bit units by the Port 4 mode register (P4IO). P4_0–P4_7 also function as input pins for internal operations (secondary function).
Page 35: P6_0-P6_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins • CLKOUT (P5_6) Output pin that outputs clock pulses specified by the peripheral control register (PRPHF) • WAIT (P5_7) BUSY signal input pin of serial Port 5 (synchronous SCI with FIFO) At reset (when the RES signal is input, the BRK instruction is executed, a watchdog timer is overflown, or an operation code trap is generated), P5 becomes a high imped- ance input.
Page 36: P7_0-P7_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P6 becomes a high imped- ance input.
Page 37: P8_0-P8_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins 2.9 P8_0–P8_7: Input/Output Pins 8-bit I/O pins of Port 8. I/O can be specified in bit units by the Port 8 mode register (P8IO). P8_0–P8_7 also function as output pins for internal operations (secondary function).
Page 38: P10_0-P10_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins • RXD4 (P9_4) Receive data for the receive side serial port 4 is output through this pin. • TXD4 (P9_5) Transmit data for the transmit side serial port 4 is input through this pin.
Page 39: P11_0-P11_7: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins • SFTCLK (P10_5) Shift clock output pin for the expansion port. • SFTDAT (P10_6) Serial data input/output pin for the expansion port. • SFTSTB (P10_7) Strobe signal output pin for externally latching serial data through the expansion port.
Page 40: P12_0, P12_1: Input/Output Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins 2.13 P12_0, P12_1: Input/Output Pins 2-bit I/O pins of Port 12. Individual bits can be specified as input or output by the Port 12 mode register (P12IO). P12_0 can also be made to function (secondary function) as an output pin for internal operation by setting the EA pin to a "L"...
Page 41: Ea: Input Pin
In the MSM66Q591/ML66Q592 flash EEPROM version, the RAM monitor function becomes enabled by setting the EA pin to a "H" level. Do not apply a high voltage (more than 5 V) to the EA pin when using the MSM66591/ ML66592 mask ROM version.
Page 42 MSM66591/ML66592 User's Manual Chapter 2 Description of Pins Table 2-1 Structure of Each Pin Pin Name Type No. Pin Name Type No. P0_0–P0_7 P8_0–P8_7 P1_0–P1_7 P9_0–P9_7 P2_0–P2_7 P10_0–P10_7 P3_0–P3_7 P11_0–P11_7 P4_0–P4_7 P12_0, P12_1 P5_0–P5_7 AI0–AI23 P6_0–P6_7 P7_0, P7_1 P7_2, P7_3 P7_4–P7_7...
Page 43: Handling Of Unused Pins
MSM66591/ML66592 User's Manual Chapter 2 Description of Pins 2.27 Handling of Unused Pins Table 2-2 shows how unused pins should be handled. Table 2-2 Handling of Unused Pins Recommended pin handling P0_0–P0_7 P1_0–P1_7 P2_0–P2_7 P3_0–P3_7 P4_0–P4_7 For input setting: "H" or "L" level P5_0–P5_5...
Page 44: Chapter 3 Cpu Architecture
Chapter 3 CPU Architecture...
Page 46: Memory Space
At reset, up to 64K bytes (small-sized memory model) can be accessed for program memory space, and up to 6K bytes (MSM66591) or 8K bytes (ML66592) for data memory space. By changing the setting of the memory size control register allocated to the SFR, the program memory space can be expanded up to 128K bytes (MSM66591) or 192K bytes (ML66592) (medium-sized memory model).
Page 47: Program Memory Space
(TSR). In the MSM66591, the entire 128K-byte area of the sum of the 64K (65536)-byte area in segment 0 and the 64K (65536)-byte area in segment 1 is the internal ROM area.
Page 48 1000H ACAL area ACAL area (2K bytes) (2K bytes) 17FFH 17FFH 1800H 1800H FFFFH FFFFH Figure 3-1(a) Memory Map of MSM66591 Program Memory Space Segment 0 Segment 1 Segment 2 0000H 0000H 0000H Vector table area (74 bytes) 0049H 004AH...
Page 49: Accessing Program Memory Space
P12_1/A17 (output: pin 91: output of code segment) also operates as a bus port. In MSM66591, the internal program fetch enable area is 00000H–1FFFDH. This means that the final address of instruction code must not exceed 1FFFDH. The final address of the table data is 1FFFFH.
Page 50 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture [Example] If the program start address by RES pin input is 0200H: Program Address Data Code 0000H (insignificant data of program start address) 0001H (significant data of program start address) Table 3-1 Vector Table List...
Page 51: Vcal Table Area
PC (even address is insignificant data, the following odd address is significant data), and program execution is started from the loaded address. If, however, the program memory space is expanded to 128K bytes (MSM66591) or 192K bytes (ML66592), the SSP is decremented by 4 because the CSR value is saved at the same time that the PC is saved.
Page 52: Acal Area
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Table 3-2 VCAL Vector Address List VCAL Table First Address [H] VCAL Instruction 004A VCAL 4AH 004C VCAL 4CH 004E VCAL 4EH 0050 VCAL 50H 0052 VCAL 52H 0054 VCAL 54H 0056 VCAL 56H...
Page 53: Data Memory Space
The pointing register area (PR: 64 bytes) and the special bit addressing area (sbafix: 64 bytes) are located in the fixed page area. In MSM66591, access to the area from 1A00H–FFFFH is inhibited since it is not located in internal RAM. However, the ROM window setting area (2000H–FFFFH) can be accessed only if the ROM window has been set.
Page 54: Special Function Register (Sfr) Area
0100H–01FFH. Internal RAM Area In the MSM66591, internal RAM is assigned to the 6K (6144)-byte area of data memory space, 0200H–19FFH. In the ML66592, internal RAM is assigned to the 8K (8192)-byte area of data memory...
Page 55: Fixed Page (Fix) Area
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Fixed Page (FIX) Area The following are assigned to the 256-byte area of data memory space, 0200H–02FFH: a pointing register (PR) area, and a special bit address area (sbafix). The pointing register area is assigned to 0200H–023FH, and it has 8 sets of the follow- ing 4 registers.
Page 56: Local Register Setting Area
The 56K (57344)-byte area from 2000H to FFFFH in the data memory space of the MSM66591 is not allocated as data memory. However, this area is used by the ROM window function if set by the ROM window setting register.
Page 57: Data Memory Access
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture 3.1.4 Data Memory Access Examples of memory access when a byte operation and a word operation are per- formed to a data memory space by an instruction are shown below. Byte Operation In the case of a byte operation, the 8-bit data indicated by the address specified by an instruction becomes the target.
Page 58: Registers
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture 3.2 Registers Registers are classified by the following functions: the arithmetic registers, control registers, pointing registers, special function registers, local registers, and segment registers. Figure 3-5 shows the configuration of each register. Arithmetic register...
Page 59: Control Register
• flags that the user can freely use (F0–2) • flags available for future expansion of CPU core functions. The user can freely use these flags in MSM66591/ML66592. (BCB0, 1, MAB) PSW can be divided into PSWH (bits 8–15) and PSWL (bits 7–0) in 8-bit units, and can perform 8-bit unit operations as well as 16-bit unit operations depending on the instruc- tion.
Page 60 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture C. Instructions for increment, decrement, and arithmetic and logic operation and com- parison to PSW or PSWH (content of PSW or PSWH is undefined after the instruc- tion is executed). If an interrupt occurs, PSW is automatically saved during an interrupt transition cycle, and automatically returns when an RTI instruction is executed.
Page 61 If MIE is set to "0", an entire maskable interrupt is disabled from the next instruction. Bit 7: sum of product operation function bank flag (MAB) Since the MSM66591/ML66592 have no sum of product operation function, MAB can be used as a user flag. Bit 5: bank common base 1 (BCB1)
Page 62: Program Counter (Pc)
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture S C B Setting of Pointing Register PR0 (0200H–0207H) PR1 (0208H–020FH) PR2 (0210H–0217H) PR3 (0218H–021FH) PR4 (0220H–0227H) PR5 (0228H–022FH) PR6 (0230H–0237H) PR7 (0238H–023FH) Program Counter (PC) The PC is a 16-bit counter that holds the address information in the segment of the program to be executed next.
Page 63: System Stack Pointer (Ssp)
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture • LRBL 8 bits specify 2K bytes of data memory space, 0200H–09FFH, in 8-byte units. LRBL LRBL 8 bits specify 2K bytes of data memory space, 0200H–09FFH, in 8-byte units. (Value x is included in instruction code.) •...
Page 64: Pointing Register (Pr)
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture 3.2.3 Pointing Register (PR) PR has 8 sets. 1 set consists of the following four 16-bit registers. • index register 1 (X1) • index register 2 (X2) • data pointer (DP) • user stack pointer (USP) PR is assigned to 0200H–023FH of the internal RAM area, and one of the 8 sets is...
Page 65: Local Registers (R, Er)
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture 3.2.4 Local Registers (R, ER) R is an 8-bit register, ER is a 16-bit register. R and ER specify 2K bytes of data memory space, 0200H–09FFH, in 8 byte units by the LRBL low-order 8 bits of the local register base.
Page 66: Segment Register
CSR can be reloaded by the FJ, FCAL, FRT, and RTI instructions and an interrupt. No other methods can reload CSR. Since in the MSM66591 CSR has only one valid bit while in the emulator for the MSM66591 CSR has two valid bits, specify either segment 0 or segment 1 when executing the FJ or FCAL instruction for MSM66591.
Page 67: Table Segment Register (Tsr)
1 to 7. Since in the MSM66591 TSR has only one valid bit while on the emulator for the MSM66591 TSR has two valid bits, be sure to write "0s" to bits 1 to 7 when writing to TSR.
Page 68: Special Function Register (Sfr)
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture 3.2.6 Special Function Register (SFR) The SFR area is a 256-byte area of data memory space, 0000H–00FFH, and the expanded SFR area is another 256-byte area of data memory space, 0100H–01FFH. SFR and expanded SFR are groups of registers that have special functions assigned, such as: •...
Page 69 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture [Note] Do not perform the following operations to SFR: A. A write operation to a read-only SFR B. A read operation to a write-only SFR C. A 16-bit operation to an 8-bit operation-only SFR D.
Page 70 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Table 3-3 SFRs Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0000 System Stack Pointer FFFF — 0001 0002 LRBL Local Register Base Undefined 0003 LRBH 0004...
Page 71 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Table 3-3 SFRs (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] S2BUF0 — 002C Undefined SCI2 Transmit/Receive Buffer Register 0 002D SCI2 Receive Buffer Register 1 S2BUF1 —...
Page 72 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Table 3-3 SFRs (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] PWM Counter 3/ PWC3/ 0056 — FFFF PWC3 Buffer Register PWC3BF 0057 PWM Counter 4/...
Page 73 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Table 3-3 SFRs (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0082 PWINTQ0L PWM Interrupt Register 0 PWINTQ0 0083 PWINTQ0H PWINTQ1L 0084 PWM Interrupt Register 1...
Page 74 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Table 3-3 SFRs (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 00AE 0000 TMR4 Buffer Register — TMR4BF 00AF 00B0 0000 — TMR5BF TMR5 Buffer Register...
Page 75 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Table 3-3 SFRs (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] Undefined 00D8 TMR0 Low-Order 4 Bits TMR0L — Undefined 00D9 TMR1 Low-Order 4 Bits TMR1L —...
Page 76 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Indicates that the R/W operation of the PWM counter/buffer is a special operation. When a read operation is performed, the value of the PWM counter (PWMCn) is read. When a write operation is performed, data is written to the PCM buffer register (PWCnBF).
Page 77 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Expanded SFR Area Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0100 Memory Size Acceptor MEMSACP "0" — 0101 Memory Size Control Register MEMSCON — 0102 0103...
Page 78 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Expanded SFR Area (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 012C SCI2 Timer Control Register S2CON — 012D SCI3 Timer Control Register S3CON — 012E...
Page 79 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Expanded SFR Area (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0158 A/D Hardware Select Register 0 — ADHSEL0 0000 0159 015A A/D Hardware Select Register 1 0000 —...
Page 80 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Expanded SFR Area (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0184 SIO5 Control Register 0 SIO5CON0 — 0185 SIO5 Control Register 1 SIO5CON1 — 0186...
Page 81 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Expanded SFR Area (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 01F0 Flash Memory Control 01F1 Register Area 01F2 (*5) 01F3 01F4 01F5 01F6 01F7 01F8...
Page 82: Addressing Mode
Access to the area from 1A00H to FFFFH in the RAM space of MSM66591 and from 2200H to FFFFH in the RAM space of ML66592 is inhibited since it is not located in internal RAM.
Page 83 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture [Byte Type] A, #12H A, VAR [Bit Type] C, A.3 A.3, LABEL B. Control Register Addressing Register contents are accessed. SSP: system stack pointer LRB: local register base PSW: program status word PSWH:...
Page 84 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture DPL: data pointer low-order byte DP*: data pointer low-order byte USPL: user stack pointer low-order byte *This register can be used only for [JRNZ DP, radr] instruction which is provided for compatibility with nX-8/100 to nX-8/400 CPU core.
Page 85: Page Addressing
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Page Addressing A. SFR Page Addressing: sfr Dadr B. FIXED Page Addressing: fix Dadr C. Current Page Addressing: off Dadr A. SFR Page Addressing SFR page addressing specifies an offset in the SFR page (0–0FFH in data memory) with one byte of instruction code.
Page 86 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture B. FIXED Page Addressing FIXED page addressing specifies an offset in the FIXED page (200H–2FFH in data memory) with one byte of instruction code. Word, byte, or bit data can be accessed at the specified address.
Page 87 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture C. Current Page Addressing Current page addressing specifies an offset in the current page (one of 256 pages in data memory specified by LRBH) with one byte of instruction code (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.
Page 88: Direct Data Addressing
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Direct Data Addressing: dir Dadr Direct page addressing specifies an address in the current physical segment of data memory (address 0–0FFFFH: 64K bytes) with two bytes of instruction code (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.
Page 89: Pointing Register Indirect Addressing
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Pointing Register Indirect Addressing A. DP/X1 Indirect Addressing: [DP],[X1] B. DP Indirect Addressing with Post-Increment: [DP+] C. DP Indirect Addressing with Post-Decrement: [DP–] D. DP/USP Indirect Addressing with 7-Bit Displacement: n7[DP],n7[USP] E. X1/X2 Indirect Addressing with 16-Bit Base: D16[X1],D16[X2] F.
Page 90 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture B. DP Indirect Addressing with Post-Increment DP indirect addressing with post-increment specifies an address in the current physical segment (address 0–0FFFFH: 64K bytes) by the contents of a pointing register (exclud- ing access inhibit area). Word, byte, or bit data can be accessed at the specified address.
Page 91 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture C. DP Indirect Addressing with Post-Decrement DP indirect addressing with post-decrement specifies an address in the current physical segment of data memory (address 0–0FFFFH: 64K bytes) by the contents of a pointing register (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.
Page 92 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture D. DP/USP Indirect Addressing with 7-Bit Displacement DP/USP indirect addressing with 7-bit displacement specifies an address in the current physical segment (address 0–0FFFFH: 64K bytes) using the contents of a pointing register as a base and adding a 7-bit displacement with sign embedded in instruction code (bits 6–0;...
Page 93 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture E. X1/X2 Indirect Addressing with 16-Bit Base X1/X2 indirect addressing with 16-bit base specifies a 2-byte (D16) base embedded in instruction code and adds it to the contents of an index register (X1 or X2) to obtain an address in the current physical segment (address 0–0FFFFH: 64K bytes).
Page 94 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture F. X1 Indirect Addressing with 8-Bit Register Displacement X1 indirect addressing with 8-bit register displacement specifies an address in the current physical segment (address 0–0FFFFH: 64K bytes) using the contents of a pointing register as a base and adding the contents of the Accumulator low byte (AL) or Local Register 0 (R0) (excluding access inhibit area).
Page 95: Special Bit Area Addressing
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Special Bit Area Addressing A. FIXED Page SBA Area Addressing: sbafix Badr B. Current Page SBA Area Addressing: sbaoff Badr A. FIXED Page SBA Area Addressing FIXED page SBA area addressing specifies a bit address in the FIXED page’s 512-bit SBA area (2C0H.0–2FFH.7).
Page 96: Rom Addressing
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture 3.3.2 ROM Addressing ROM addressing specifies addressing of program variables in ROM space. The modes provided are immediate addressing, table data addressing, and program code address- ing. Immediate Addressing Immediate addressing specifies access of immediate data embedded in instruction code.
Page 97 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture [Byte Type] A, VAR CMPCB A, VAR B. RAM Addressing Indirect Table Addressing RAM addressing indirect table addressing uses the word data specified by RAM addressing as a pointer to the table segment specified by TSR. Word (16-bit) calcula- tions are used to generate the address, with overflows ignored.
Page 98: Program Code Addressing
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture Program Code Addressing Program code addressing specifies access of the current program code in ROM space. These modes are used as operands of branch instructions. A. NEAR Code Addressing: Cadr B. FAR Code Addressing: Fadr C.
Page 99 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture [Example of Use] LABEL DJNZ R0, LABEL LT, LABEL D. ACAL Code Addressing ACAL code addressing specifies an address in the ACAL area (1000H–17FFH: 2K bytes) in the current code segment with 11 bits of instruction code. This addressing can be used only with ACAL instructions.
Page 100: Rom Window Addressing
MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture ROM Window Addressing ROM window addressing accesses table data in ROM space using RAM addressing. This mode reads data in the table segment specified by TSR using data segment window opened by the program. (See "ROM Window Function.") Data memory addressing is permitted in the ROM window area, but results are not guaranteed if an instruction that writes to the ROM window is executed.
Page 101 MSM66591/ML66592 User's Manual Chapter 3 CPU Architecture 3-56...
Page 102: Chapter 4 Cpu Control Functions
Chapter 4 CPU Control Functions...
Page 104: Standby Function
• Standby function • Reset function 4.1 Standby Function The MSM66591/ML66592 standby function has two types of operation modes: • HALT mode: stops the clock supply CPU by software • STOP mode: stops the original oscillation clock supply by software Each mode is set by: •...
Page 105 MSM66591/ML66592 User's Manual Chapter 4 CPU Control Functions Table 4-1 Standby Modes Standby Mode HALT Mode STOP Mode (*1) • Set bit 1 (HLT) of • Set bit 0 (STP) of • Set bit 0 (STP) of SBYCON to "1"...
Page 106: Standby Control Register (Sbycon)
MSM66591/ML66592 User's Manual Chapter 4 CPU Control Functions 4.1.1 Standby Control Register (SBYCON) SBYCON is a 5-bit register that controls standby functions. The stop code acceptor (STPACP) is an acceptor used to set STOP mode. Figure 4-1 shows the configuration of SBYCON.
Page 107: Operation In Each Standby Mode
4.1.2 Operation in Each Standby Mode HALT Mode The MSM66591/ML66592 enter HALT mode if HLT (bit 1) of SBYCON is set to "1". In HALT mode, the original oscillation clock operates, and the TBC, the WDT, the flexible timer, serial ports, etc. also operate. However the clock supply to the CPU stops, therefore instructions are not executed.
Page 108: Stop Mode
MSM66591/ML66592 User's Manual Chapter 4 CPU Control Functions STOP Mode Writing n5H and nAH (n = 0–F) consecutively to STPACP will set the stop code accep- tor to "1". Setting the STP bit of SBYCON to "1" at that point will set the device in stop mode.
Page 109: Reset Function
OST0 and OST1 as the number of clock cycles. Figure 4-2 STOP Mode Timing (when cleared by an interrupt) 4.2 Reset Function The MSM66591/ML66592 become reset status by the following four factors: • RES pin input becomes "L" level • BRK (break) instruction is executed •...
Page 110 MSM66591/ML66592 User's Manual Chapter 4 CPU Control Functions External Internal Reset Processing Circuit SW and R are needed for manual reset. Figure 4-3 Reset Pin Connection Example Table 4-2 Output Pin Status at Reset P2–P6, P7_0, P7_1, P7_2, P7_3 P7_2, P7_3 Name P7_4–P7_7, P8–P11,...
Page 111 MSM66591/ML66592 User's Manual Chapter 4 CPU Control Functions...
Page 112: Chapter 5 Memory Control Functions
Chapter 5 Memory Control Functions...
Page 114: Rom Window Function
64K bytes of program memory space. However, in the MSM66591 "2", "4", and "8" are the only values that can be specified. Therefore, the area for which the ROM window can be set is either 2000H–0FFFFH, 4000H–0FFFFH, or 8000H–0FFFFH.
Page 115 ROMWIN, however, can be read any number of times. [Note] In MSM66591 do not write any other value than 2H, 4H, and 8H to the low-order 4 bits of ROMWIN. In ML66592 do not write any other value than 3H, 4H, and 8H to the low-order 4 bits of...
Page 116: Ready Function
Chapter 5 Memory Control Functions 5.2 READY Function The MSM66591/ML66592 can specify the wait cycle (ROM: 0 to 3 cycles) to insert during external memory access, so that memory that has a slow access speed can be connected. The ROM READY control register (ROMRDY) specifies the number of wait cycles.
Page 117 MSM66591/ML66592 User's Manual Chapter 5 Memory Control Functions...
Page 118: Chapter 6 Port Functions
Chapter 6 Port Functions...
Page 120: Hardware Configuration Of Each Port
(secondary functions) are assigned to most ports. 6.1 Hardware Configuration of Each Port The MSM66591/ML66592 ports (P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10, P11, P12) are classified into the following 5 types according to function.
Page 121 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-1 Port Function List Port Name Name Type Qty Secondary Function OE Control Port 0 P0_0–P0_7 External memory address/data: AD0–AD7 (I/O) Port 1 P1_0–P1_7 External memory address: A8–A15 (Output) Port 2 P2_0–P2_7 Double buffer RTO output: RTO4–RTO11 (Output)
Page 122 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-1 Port Function List (continued) OE Control Port Name Name Type Qty Secondary Function P10_0, P10_1 Double buffer RTO output: RTO12, 13 (Output) P10_2, P10_3 CAP event input: CPA14, CAP15 (Input) P10_4...
Page 123: Configuration Of Type A (P0_0-P0_7, P1_0-P1_7, P12_0)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.1.1 Configuration of Type A (P0_0–P0_7, P1_0–P1_7, P12_0) Type A ports automatically take their secondary function when the EA pin is set to "L" level. They function as address output pins and data I/O pins for external program memory access.
Page 124: Configuration Of Type B
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.1.2 Configuration of Type B (P2_0 – P2_7, P3_0 – P3_3, P7_4 – P7_7, P8_0 – P8_7, P10_0–P10_4) Some of the type B ports function as high-order address output when the external data memory is accessed and the other ports act as secondary function input and output pins, according to the specification of the secondary function control register (PmSFn).
Page 125: Configuration Of Type C
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.1.3 Configuration of Type C (P3_4–P3_7, P4_0–P4_7, P5_0–P5_7, P6_0–P6_7, P7_2, P7_3, P9_0–P9_7, P10_5–P10_7, P11_0–P11_3) Type C ports function as the output pins of secondary functions, or as input pins of secondary functions according to the specification of the secondary function control register (PmSFn).
Page 126: Configuration Of Type D (P7_0, P7_1, P11_4-P11_7)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.1.4 Configuration of Type D (P7_0, P7_1, P11_4–P11_7) Type D ports function as I/O pins without secondary functions. Figure 6-4 shows the configuration of Type D ports. PmIOn Pm_n Pm_n m = 7...
Page 127: Port Control Registers
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.2 Port Control Registers The MSM66591/ML66592 have 3 types of port control registers. • port data register (Pn: n = 0–12) • port mode register (PnIO: n = 0–12) • port secondary function control register (PnSF: n = 2–10) These registers are allocated as SFRs.
Page 128 MSM66591/ML66592 User's Manual Chapter 6 Port Functions PnSF is assigned to SFR, and the content of P2SF–P10SF becomes 00H, and all ports are set to primary functions at reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated).
Page 129 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-2 Port Control SFRs Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0010 Port 0 Data Register — 0011 Port 1 Data Register — 0012 Port 2 Data Register —...
Page 130: Port 0 (P0)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.3 Port 0 (P0) Port 0 (P0_0–P0_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 0 mode register (P0IO). In addition to its port function, Port 0 is assigned a secondary function (low-order address output and data input of external program memory).
Page 131: Port 1 (P1)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.4 Port 1 (P1) Port 1 (P1_0–P1_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 1 mode register (P1IO). In addition to the port function, a secondary function (high address output of external program memory) is assigned to Port 1.
Page 132: Port 2 (P2)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.5 Port 2 (P2) Port 2 (P2_0–P2_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 2 mode register (P2IO). In addition to the port function, a secondary function (real-time output, etc.) is assigned to Port 2.
Page 133 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-3 shows the content of the data that is read when a read instruction is executed to P2, according to the content of P2IO and P2SF. If an arithmetic instruction, incre- ment instruction, or instruction of that type (read-modify-write instruction) is executed to P2, the content of the pin or port data register is read according to specification by P2IO (when reading), and data is written to the port data register (when writing).
Page 134: Port 3 (P3)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.6 Port 3 (P3) Port 3 (P3_0–P3_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 3 mode register (P3IO). In addition to the port function, a secondary function (real-time output, etc.) is assigned to Port 3.
Page 135 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-4 shows the content of the data that is read when a read instruction is executed to P3 according to the content of P3IO and P3SF. If an arithmetic instruction, increment instruction, or instruction of that type (read-modify-write instruction) is executed to P3, the content of the pin or port data register is read according to specification by P3IO (when reading), and data is written to the port data register (when writing).
Page 136: Port 4 (P4)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.7 Port 4 (P4) Port 4 (P4_0–P4_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 4 mode register (P4IO). In addition to the port function, a secondary function (transition detector input) is assigned to Port 4.
Page 137 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-5 shows the content of the data that is read when a read instruction is executed to P4 according to the content of P4IO and P4SF. If an arithmetic instruction, increment instruction, or instruction of that type (read-modify-write instruction) is executed to Port 4, the content of the pin or port data register is read according to specification by P4IO (when reading), and data is written to the port data register (when writing).
Page 138: Port 5 (P5)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.8 Port 5 (P5) Port 5 (P5_0–P5_7) is a 8-bit I/O port. Input or output can be specified for each bit by the Port 5 mode register (P5IO). In addition to the port function, a secondary function (serial interface with FIFO) is assigned to Port 5.
Page 139 MSM66591/ML66592 User's Manual Chapter 6 Port Functions If a read instruction is executed to P5 in which the input is specified (P5IOn = "0") by P5IO, the content of the pin is read. If a read instruction is executed to P5 in which the output is specified (P5IOn = "1"), the content of the port data register is read.
Page 140: Port 6 (P6)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.9 Port 6 (P6) Port 6 (P6_0–P6_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 6 mode register (P6IO). In addition to the port function, a secondary function (external interrupt input, etc.) is assigned to Port 6.
Page 141 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-6 shows the content of the data that is read when a read instruction is executed to P6 according to the content of P6I0 and P6SF. If an arithmetic instruction, increment instruction, or instruction of that type (read-modify-write instruction) is executed to Port 6, the content of the pin or port data register is read according to specification by P6IO (when reading), and data is written to the port data register (when writing).
Page 142: Port 7 (P7)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.10 Port 7 (P7) Port 7 (P7_0–P7_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 7 mode register (P7IO). In addition to the port function, a secondary function (output of the strobe signal for the external memory, etc) is assigned to Port 7.
Page 143 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-7 shows the content of the data that is read when a read instruction is executed to P7 according to the content of P7IO and P7SF. If an arithmetic instruction, increment instruction, or instruction of that type (read-modify-write instruction) is executed to P7, the content of the pin or port data register is read according to specification by P7IO (when reading), and data is written to the port data register (when writing).
Page 144: Port 8 (P8)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.11 Port 8 (P8) Port 8 (P8_0–P8_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 8 mode register (P8IO). In addition to the port function, a secondary function (PWM output) is assigned to Port 8.
Page 145 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-8 shows the content of the data that is read when a read instruction is executed to P8 according to the content of P8I0 and P8SF. If an arithmetic instruction, increment instruction, or instruction of that type (read-modify-write instruction) is executed to P8, the content of the pin or port data register is read according to specification by P8IO when reading, and data is written to the port data register when writing.
Page 146: Port 9 (P9)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.12 Port 9 (P9) Port 9 (P9_0 – P9_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 9 mode register (P9IO). In addition to the port function, a secondary function (serial port I/O, etc) is assigned to Port 9.
Page 147 MSM66591/ML66592 User's Manual Chapter 6 Port Functions If a read instruction is executed to P9 in which the input is specified (P9IOn = "0") by P9IO, the content of the pin is read. If a read instruction is executed to P9 in which the output is specified (P9IOn = "1"), the content of the port data register is read.
Page 148: Port 10 (P10)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.13 Port 10 (P10) Port 10 (P10_0–P10_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 10 mode register (P10IO). In addition to the port function, a secondary function (real time output, etc) is assigned to Port 10.
Page 149 MSM66591/ML66592 User's Manual Chapter 6 Port Functions Table 6-9 shows the content of the data that is read when a read instruction is executed to P10 according to the content of P10I0 and P10SF. If an arithmetic instruction, increment instruction, or instruction of that type (read-modify-write instruction) is ex-...
Page 150: Port 11 (P11)
MSM66591/ML66592 User's Manual Chapter 6 Port Functions 6.14 Port 11 (P11) Port 11 (P11_0–P11_7) is an 8-bit I/O port. Input or output can be specified for each bit by the Port 11 mode register (P11IO). In addition to the port function, a secondary function (RAM monitor function) is assigned to port 11.
Page 151: Port 12 (P12)
ML66592, address 16 and 17 output of external program memory) is assigned to Port 12. If the EA pin is set to "L" level, in MSM66591 P12_0 operates as an address bus (address 16 output pin) of the external program memory, and in ML66592 P12_0 and P12_1 operate as address buses (address 16 and 17 output pins) of the external program memory.
Page 152: Chapter 7 Output Pin Control Pin (Oe)
Chapter 7 Output Pin Control Pin (OE)
Page 154 Chapter 7 Output Pin Control Pin (OE) 7. Output Pin Control Pin (OE) The MSM66591/ML66592 have an OE pin (pin 71) to control the output of 47 pins, P0, P1, P2, P3_0–P3_3, P7_4–P7_7, P8, P10_0–P10_4, P12_0, and P12_1. If the OE pin is in "H" level when P0, P1, P2, P3_0–P3_3, P7_4–P7_7, P8, P10_0–...
Page 155 MSM66591/ML66592 User's Manual Chapter 7 Output Pin Control Pin (OE)
Page 156: Chapter 8 Clock Generation Circuit
Chapter 8 Clock Generation Circuit...
Page 158 The clock generation circuit generates the master clock pulse (CLK) necessary for the MSM66591/ML66592. In other words, the clock generation circuit multiplies the clock generated by the oscillation circuit by a factor of 2, then supplies the obtained clock to the MSM66591/ML66592.
Page 159 MSM66591/ML66592 User's Manual Chapter 8 Clock Generation Circuit The clock generation circuit can be stopped by STOP mode so that power consumption is further decreased. If STOP mode is cleared by an interrupt request, the master clock pulse is transferred when the number of clocks specified by OST0 and OST1 (bits 4 and 5) of SBYCON have elapsed after oscillation starts.
Page 160: Chapter 9 Time Base Counter (Tbc)
Chapter 9 Time Base Counter (TBC)
Page 162 Chapter 9 Time Base Counter (TBC) 9. Time Base Counter (TBC) The MSM66591/ML66592 time base counter (TBC) is an 8-bit counter that uses as its input clock an overflow of the 4-bit auto-reload timer. The 4-bit auto-reload timer uses as its input the master clock pulse (CLK) generated by multiplying the original oscillation clock by 2.
Page 163: 1/N Counter
Chapter 9 Time Base Counter (TBC) 9.1 1/n Counter The MSM66591/ML66592 have a 4-bit auto-reload timer that uses a CLK as the input clock, therefore the same clock pulse (TBCCLK) can be supplied to TBC, even if the original oscillation frequency is changed.
Page 164: Chapter 10 Watchdog Timer (Wdt)
Chapter 10 Watchdog Timer (WDT)
Page 166: Wdt Control Register (Wdtcon)
MSM66591/ML66592 User's Manual Chapter 10 Watchdog Timer (WDT) 10. Watchdog Timer (WDT) The watchdog timer (WDT) is a 9-bit counter that uses the overflow (1/256 TBCCLK or 1/512 TBCCLK) of the time base counter (TBC) as the input clock. It resets the device when program runaway is detected.
Page 167: Time Until Overflow Of Wdt
∆t = (1/f) µsec ¥ n ¥ 2 occurs, since the content of TBC does not change. When the master clock of the MSM66591 is 24 MHz and n = 8, the result is = 43.69 msec ∆t = 85.33 µsec When the master clock of the ML66592 is 28 MHz and n = 8, the result is = 37.45 msec...
Page 168 MSM66591/ML66592 User's Manual Chapter 10 Watchdog Timer (WDT) Progress of Program Content of WDT 3CH write C3H write 3CH write C3H write WDT start WDT clear to "0" WDT clear to "0" WDT clear to "0" 000H within within within...
Page 169 MSM66591/ML66592 User's Manual Chapter 10 Watchdog Timer (WDT) WDT is cleared to "0" WDT is cleared to "0" by writing 3CH to WDT by writing 3CH to WDT WDT is cleared to "0" WDT is cleared to "0" by writing C3H to WDT...
Page 170: Chapter 11 Flexible Timer (Ftm)
Chapter 11 Flexible Timer (FTM)
Page 172 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11. Flexible Timer (FTM) The MSM66591/ML66592 flexible timer (FTM) consists of a 20-bit counter, a 16-bit counter, four 20-bit registers, fourteen 16-bit registers, control registers, and other components. The functions of the timer include: •...
Page 173 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Counter Part TM0 (20-bit) TM1 (16-bit) TMCON (8-bit) Counter Selection Part TMSEL (16-bit) TMSEL2 (8-bit) Type A1 Register Modules TMR0–TMR3 TMRL0–TMRL3 P3_4/CAP0–P3_7/CAP3 CAPCON EVDV0–EVDV3 EVDV0BF–EVDV3BF EVNTCONL, EVNTCONH Type B Register Modules TMR4–TMR13 P2_0/RTO4–P2_7/RTO11...
Page 174 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Table 11-1 List of SFRs for Controlling FTM Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 008A Timer Register 0 Undefined — TMR0 008B 008C Timer Register 1 Undefined —...
Page 175 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Table 11-1 List of SFRs for Controlling FTM (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 00B6 TMR8 Buffer Register 0000 — TMR8BF 00B7 00B8...
Page 176 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Table 11-1 List of SFRs for Controlling FTM (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] Timer Control Register 00DC TMCON — Event Control Register 2...
Page 177: Configuration Of Counter Part
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.1 Configuration of Counter Part The counter part consists of a 20-bit freerun counter (TM0, TM0L), a 16-bit freerun counter (TM1), an input clock selector for each freerun counter, a timer data sequencer to output as TMD the high-order 16-bits of TM0 and the TM1 values alternately at one- CLK intervals, and a control register (TMCON) to control the operation of TM0/TM1.
Page 178 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) The 4-bit output (TM0L4) of TM0L is connected to the timer register module type A1. The high-order 16-bit output of TM0, and the 16-bit output of TM1 are time-sharing outputs (TMD) by CLK, at the timer data sequencer, and are connected to each timer register module.
Page 179: Counter Selection Part
Chapter 11 Flexible Timer (FTM) 11.2 Counter Selection Part The MSM66591/ML66592 have 18 timer register modules. Each timer register module can be connected to either one of the two freerun counters (TM0 and TM1). The selection is specified by the timer setting register (TMSEL) and timer setting register 2 (TMSEL2).
Page 180 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) TMSEL (bits 0–7) TMR0 is connected to TM0 TMR0 is connected to TM1 TMR1 is connected to TM0 TMR1 is connected to TM1 TMR2 is connected to TM0 TMR2 is connected to TM1...
Page 181: Type A1 Register Modules (Tmr0-Tmr3)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.3 Type A1 Register Modules (TMR0–TMR3) The MSM66591/ML66592 have four sets of type A1 register modules (TMR0–TMR3). The configuration is the same for all the sets, except for the address of registers on SFR.
Page 182: Capture Control Register (Capcon)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), TMR0–TMR3 and TMR0L– TMR3L become undefined. Capture Control Register (CAPCON) CAPCON is a 16-bit register that specifies the valid edge of a signal that is input to the CAP0 (P3_4)–CAP3 (P3_7) pins, CAP14 (P10_2), CAP15 (P10_3), and, when TMR16...
Page 183: Event Control Registers (Evntconl, Evntconh)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Event Control Registers (EVNTCONL, EVNTCONH) EVNTCONL and EVNTCONH are 8-bit registers that specify the dividing ratio (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) of the valid edge that is specified by the CAPCON of the signal that is input to CAP0 (P3_4)–CAP3 (P3_7) pins.
Page 184 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) EVNTCONH — T3EV2 T3EV1 T3EV0 — T2EV2 T2EV1 T2EV0 T2EV Dividing ratio of valid edge of CAP2 pin 2 1 0 0 0 0 1/1 division 0 0 1 1/2 division 0 1 0...
Page 185: Event Dividing Counters 0-3 (Evdv0-Evdv3)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Event Dividing Counters 0–3 (EVDV0–EVDV3) EVDV0–EVDV3 are 6-bit counters that count the valid edge (specified by CAPCON) input to CAP0–CAP3 pins for the value specified by EVNTCONL and EVNTCONH. Figure 11-11 shows the configuration of EVDVn (n = 0–3).
Page 186: Operation Of Type A1 Register Modules (Tmr0-Tmr3)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.3.2 Operation of Type A1 Register Modules (TMR0–TMR3) If the valid edge specified by CAPCON is input to CAP0–CAP3 pins when the TM specified by TMSEL is in RUN status, the divider divides the pulse in the dividing ratio specified by EVNTCON.
Page 187: Capture Pin Dividing Circuit
Operation to Switch Dividing Ratio Since the dividing ratio is programmable, the dividing operation may differ, depending on the timing that changes the dividing ratio. In this case, the MSM66591/ML66592 operate as follows: 1) When the dividing ratio is changed from 1/N to 1/M (N > M), if a valid edge is input to a capture pin when: •...
Page 188: Type A2 Register Modules (Tmr14, Tmr15)
Chapter 11 Flexible Timer (FTM) 11.4 Type A2 Register Modules (TMR14, TMR15) The MSM66591/ML66592 have two sets of type A2 register modules (TMR14, TMR15). The configuration is the same for the two sets, except for the address of registers on SFR.
Page 189: Capture Control Register (Capcon)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Capture Control Register (CAPCON) CAPCON is a 16-bit register that specifies the valid edge of a signal that is input to the CAP0 (P3_4)–CAP3 (P3_7) pins, CAP14 (P10_2), CAP15 (P10_3), and, when TMR16 and TMR17 are in CAP mode, to FTM16 (P10_4) and FTM17A (P3_0) pins.
Page 190: Event Control Register 2 (Evntcon2)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Event Control Register 2 (EVNTCON2) EVNTCON2 is an 8-bit register that specifies the dividing ratio (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) of the valid edge that is specified by the CAPCON of the signal that is input to CAP14 (P10_2) and CAP15 (P10_3) pins.
Page 191: Event Dividing Counters 14, 15 (Evdv14, Evdv15)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Event Dividing Counters 14, 15 (EVDV14, EVDV15) EVDV14 and EVDV15 are 6-bit counters that count the valid edge (specified by CAPCON) input to CAP14 and CAP15 pins for the value specified by EVNTCON2.
Page 192: Operation Of Type A2 Register Modules (Tmr14, Tmr15)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.4.2 Operation of Type A2 Register Modules (TMR14, TMR15) If the valid edge specified by CAPCON is input to CAP14 or CAP15 pin when the TM specified by TMSEL is in RUN status, the divider divides the pulse in the dividing ratio specified by EVNTCON2.
Page 193: Capture Pin Dividing Circuit
Operation to Switch Dividing Ratio Since the dividing ratio is programmable, the dividing operation may differ, depending on the timing that changes the dividing ratio. In this case, the MSM66591/ML66592 operate as follows: 1) When the dividing ratio is changed from 1/N to 1/M (N > M), if the valid edge is input to a capture pin when: •...
Page 194: Type B Register Modules (Tmr4-Tmr13)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.5 Type B Register Modules (TMR4–TMR13) The MSM66591/ML66592 have 10 sets of register modules type B (TMR4–TMR13). The configuration is the same for these 10 sets, except for the address of registers on SFR.
Page 195: Timer Registers (Tmr4-Tmr13)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Timer Registers (TMR4–TMR13) A timer register (TMR4–TMR13) consists of 16 bits. TMR4–TMR13 are constantly compared with the counter values specified by TMSEL, and if they match, the contents of TMR4BF, TMR13BF are loaded to the timer registers.
Page 196 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) RTOCON4–RTOCON13 — — — — — TnBF1 TnBF0 TnOUT The content of this flag is output to an RTOn pin. If the selected counter value and the TMRn value match, the content of this flag is loaded to TnOUT.
Page 197: Operation Of Type B Register Modules (Tmr4-Tmr13)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.5.2 Operation of Type B Register Modules (TMR4–TMR13) Type B register modules have a double-buffer real-time output function. When the TM specified by TMSEL is in RUN status, TMR4–TMR13 are constantly compared with the specified counter value, and if they match, an interrupt request by real-time output is generated, and the content of TMR4BF–TMR13BF are loaded to TMR4–TMR13.
Page 198: Type D Register Module (Tmr17)
Chapter 11 Flexible Timer (FTM) 11.6 Type D Register Module (TMR17) The MSM66591/ML66592 have one set of type D register module (TMR17). 11.6.1 Configuration of Type D Register Module (TMR17) Type D register module has three types of functions: 4-port output RTO, RTO, and 16- bit capture input.
Page 199 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) CAP17 Timing T17SEL Controller 17 T17BF0 T17OUT TMDS FTM17A Interrupt Comparison Circuit request T17BFA T17OUTA TMR17 T17BFB T17OUTB FTM17B CAP17 FTM17C T17BFC T17OUTC T17BFD T17OUTD FTM17D T17CER Figure 11-23 Configuration of Type D Register Module...
Page 200: Timer Register (Tmr17)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Timer Register (TMR17) A timer register consists of 16 bits (TMR17). In the case of RTO operation, TMR17 is constantly compared with the counter value specified by TMSEL2. In the case of CAP operation, the counter value specified by TMSEL2 is loaded when a pin event is generated.
Page 201 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) RTOCON17 — — — — — T17CER T17BF0 T17OUT When TMR17 is in RTO mode, the content of this flag is output to a FTM17 pin. When TMR17 is in RTO mode, if the...
Page 202: Tmr Mode Register (Tmrmode)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) TMR Mode Register (TMRMODE) TMR mode register (TMRMODE) consists of 3 bits. TMRMODE sets the operational functions of TMR16 and TMR17. TMRMODE can be read/written by the program. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), TMRMODE becomes F2H, TMR16 is specified to RTO mode, and TMR17 is specified to 4-port output RTO mode.
Page 203: Capture Control Register (Capcon)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Capture Control Register (CAPCON) CAPCON is a 16-bit register that specifies the valid edge of a signal that is input to the CAP0 (P3_4)–CAP3 (P3_7) pins, CAP14 (P10_2), CAP15 (P10_3), and, when TMR16 and TMR17 are in CAP mode, to FTM16 (P10_4) and FTM17A (P3_0) pins.
Page 204: Operation Of Type D Register Module (Tmr17)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.6.2 Operation of Type D Register Module (TMR17) Three functions can be selected for a type D register module by TMRMODE. • real-time output mode (RTO) • 4-port real-time output mode (4-port RTO) •...
Page 205: Operation In 4-Port Output Real-Time Output Mode (4-Port Rto)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Operation in 4-Port Output Real-time Output Mode (4-Port RTO) When the TM specified by TMSEL2 is in RUN status, TMR17 is constantly compared with the specified counter value, and if they match, an interrupt request by a real-time output is generated, and the contents of T17BFA–T17BFD (bits 4–7) of RTO4CON are...
Page 206: Operation In Cap Mode
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Operation in CAP Mode When the TM specified by TMSEL2 is in RUN status, if the valid edge specified by CAPCON is input to FTM17A pin, an interrupt request by a capture event is generated, and at the same time, the content counter specified by TMSEL2 is loaded to TMR17.
Page 207: Type E Register Module (Tmr16)
Chapter 11 Flexible Timer (FTM) 11.7 Type E Register Module (TMR16) The MSM66591/ML66592 have one set of type E register module (TMR16). 11.7.1 Configuration of Type E Register Module (TMR16) Type E register module has two types of functions: RTO and 16-bit capture input.
Page 208: Timer Register (Tmr16)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Timer Register (TMR16) A timer register consists of 16 bits (TMR16). In the case of RTO operation, TMR16 is constantly compared with the counter value specified by TMSEL2. In the case of CAP mode, the counter value specified by TMSEL2 is loaded to the timer register when a pin event is generated.
Page 209: Tmr Mode Register (Tmrmode)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) TMR Mode Register (TMRMODE) TMR mode register (TMRMODE) consists of 3 bits. TMRMODE sets the operational functions of TMR16 and TMR17. TMRMODE can be read/written by the program. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), TMRMODE becomes F2H, TMR16 is specified to RTO mode, and TMR17 is specified to 4-port output RTO mode.
Page 210: Capture Control Register (Capcon)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) Capture Control Register (CAPCON) CAPCON is a 16-bit register that specifies the valid edge of a signal that is input to the CAP0 (P3_4)–CAP3 (P3_7) pins, CAP14 (P10_2), CAP15 (P10_3), and, when TMR16 and TMR17 are in CAP mode, to FTM16 (P10_4) and FTM17A (P3_0) pins.
Page 211: Operation Of Type E Register Module (Tmr16)
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.7.2 Operation of Type E Register Module (TMR16) Two functions can be selected for a type E register module by TMRMODE. • real-time output mode (RTO) • 16-bit capture mode (CAP) Operation in Real-time Output Mode (RTO)
Page 212: Rto Mode Output Timing Changes
MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11.8 RTO Mode Output Timing Changes Figure 11-35 shows an example of RTO mode output timing changes of register modules type B, type D, and type E. Figure 11-35 uses the RTO output function of type B register module as an example.
Page 213 MSM66591/ML66592 User's Manual Chapter 11 Flexible Timer (FTM) 11-42...
Page 214: Chapter 12 General-Purpose 8-Bit Timer Function
Chapter 12 General-Purpose 8-Bit Timer Function...
Page 216 MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function 12. General-Purpose 8-Bit Timer Function The MSM66591/ML66592 have one general-purpose 8-bit timer (GTM) and one general-purpose 8-bit event counter (GEVC). Table 12-1 lists the GTM control SFRs. Table 12-1 GTM Control SFRs...
Page 217: General-Purpose 8-Bit Timer (Gtm)
MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function 12.1 General-Purpose 8-Bit Timer (GTM) The general-purpose 8-bit timer consists of an 8-bit timer counter (GTMC), an 8-bit timer register (GTMR) that stores the reload values of GTMC, and a general-purpose 8- bit timer control register (GTMCON) that controls operations.
Page 218: General-Purpose 8-Bit Timer Counter (Gtmc)
MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function General-Purpose 8-Bit Timer Counter (GTMC) The GTMC is an 8-bit counter that generates an interrupt request when an overflow occurs, and at the same time, the content of the general-purpose 8-bit timer register (GTMR) is loaded.
Page 219 MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function GTMCON GEVRUN GEVCK — — GTMRUN GTMCK2 GTMCK1 GTMCK0 GTMCK Count Clock of GTMC 2 1 0 0 0 0 1/2 TBCCLK 0 0 1 1/4 TBCCLK 0 1 0 1/8 TBCCLK...
Page 220: General-Purpose 8-Bit Timer Interrupt Control Register (Gtintcon)
MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) GTINTCON is an 8-bit register that controls the generation of interrupts for the general- purpose 8-bit timer and general-purpose 8-bit event counter. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), GTINTCON becomes F0H.
Page 221: General-Purpose 8-Bit Event Counter (Gevc)
MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function 12.2 General-Purpose 8-Bit Event Counter (GEVC) The general-purpose 8-bit event counter consists of an 8-bit counter (GEVC), and an 8- bit general-purpose 8-bit timer control register (GTMCON) that controls operations. Figure 12-4 shows the configuration of GEVC.
Page 222: General-Purpose 8-Bit Timer Interrupt Control Register (Gtintcon)
MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) GTINTCON is an 8-bit register that controls the generation of interrupts for the general- purpose 8-bit timer and general-purpose 8-bit event counter. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), GTINTCON becomes F0H.
Page 223 MSM66591/ML66592 User's Manual Chapter 12 General-Purpose 8-Bit Timer Function 12-8...
Page 224: Chapter 13 Pwm Functions
Chapter 13 PWM Functions...
Page 226 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions 13. PWM Functions The MSM66591/ML66592 have 12 channels of PWM functions. PWM consists of a count clock dividing circuit, a 16-bit counter, three 16-bit registers, various control registers, etc. If the master clock is 24 MHz, a 10.6 msec (valid bit length: 8 bits) to 838.9 msec (valid bit length: 16 bits) cycle can be selected by combining the input clock of the PWM counter and a valid bit length.
Page 227 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions Table 13-1 PWM Control SFRs Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0050 PWM Counter 0/ PWC0/ FFFF — 0051 PWC0 Buffer Register PWC0BF 0052 PWM Counter 1/...
Page 228 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions Table 13-1 PWM Control SFRs (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0080 PWRUNL PWMRUN Register PWRUN 0081 PWRUNH 0082 PWINTQ0L PWM Interrupt Register 0...
Page 229: Configuration Of Pwm
MSM66591/ML66592 User's Manual Chapter 13 PWM Functions 13.1 Configuration of PWM The MSM66591/ML66592 have 12 sets of PWM functions (PWM0–PWM11). PWM0– PWM11 have the same configuration except for the SFR address. PWM consists of 16-bit counters (PWC0–PWC11), 16-bit counter buffer registers (PWC0BF–PWC11BF), 16-bit registers (PWR0–PWR11), 16-bit buffer registers...
Page 230: Pwm Registers (Pwr0-Pwr11)
MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWM Registers (PWR0–PWR11) PWR0–PWR11 are 16-bit registers that store the duty values to output. If PWC0– PWC11 underflow, the contents of the 16-bit PWM buffer register are loaded to PWR0– PWR11. PWR0–PWR11 can be read, but cannot be written, by the program. However, if the corresponding PWnRUN bit is "0"...
Page 231 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWCON0 PW1ACT PW1CK2 PW1CK1 PW1CK0 PW0ACT PW0CK2 PW0CK1 PW0CK0 PW0CK Count Clock of PWC0 Master clock TBCCLK 1/2 TBCCLK 1/4 TBCCLK 1/8 TBCCLK 1/16 TBCCLK PWM0 high active status PWM0 low active status...
Page 232 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWCON2 PW5ACT PW5CK2 PW5CK1 PW5CK0 PW4ACT PW4CK2 PW4CK1 PW4CK0 PW4CK Count Clock of PWC4 Master clock TBCCLK 1/2 TBCCLK 1/4 TBCCLK 1/8 TBCCLK 1/16 TBCCLK PWM4 high active status PWM4 low active status...
Page 233 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWCON4 PW9ACT PW9CK2 PW9CK1 PW9CK0 PW8ACT PW8CK2 PW8CK1 PW8CK0 PW8CK Count Clock of PWC8 Master clock TBCCLK 1/2 TBCCLK 1/4 TBCCLK 1/8 TBCCLK 1/16 TBCCLK PWM8 high active status PWM8 low active status...
Page 234: Pwmrun Register (Pwrun)
MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWMRUN Register (PWRUN) PWRUN consists of an 8-bit register (PWRUNL) and a 4-bit register (PWRUNH). It controls the run/stop of PWC0–PWC11 counter operations. Figure 13-8 shows the configuration of PWRUNL, and Figure 13-9 the configuration of PWRUNH.
Page 235: Pwm Interrupt Registers (Pwintq0, Pwintq1)
MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWM Interrupt Registers (PWINTQ0, PWINTQ1) Each interrupt request of PWM0–PWM11 is generated when an underflow of PWC0– PWC11 is generated or when the content of PWC0–PWC11 and that of PWR0–PWR11 match. The interrupt vectors corresponding to the interrupt requests generated by PWM0–...
Page 236 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWINTQ0L QPW7 QPW6 QPW5 QPW4 QPW3 QPW2 QPW1 QPW0 0 PWC0 underflow generation: no 1 PWC0 underflow generation: yes 0 PWC1 underflow generation: no 1 PWC1 underflow generation: yes 0 PWC2 underflow generation: no...
Page 237 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWINTQ1L QPWR7 QPWR6 QPWR5 QPWR4 QPWR3 QPWR2 QPWR1 QPWR0 0 Match of PWC0 and PWR0: no 1 Match of PWC0 and PWR0: yes 0 Match of PWC1 and PWR1: no 1 Match of PWC1 and PWR1: yes...
Page 238: Pwm Interrupt Enable Registers (Pwinte0, Pwinte1)
MSM66591/ML66592 User's Manual Chapter 13 PWM Functions [10] PWM Interrupt Enable Registers (PWINTE0, PWINTE1) PWINTE0 and PWINTE1 are 16-bit registers. PWINTE0 consists of 8-bit registers PWINTE0L and PWINTE0H, and PWINTE1 consists of 8-bit registers PWINTE1L and PWINTE1H. PWINTE0 is a register that controls enable/disable of the interrupt request by PWC0–PWC11 undferflow generation.
Page 239 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWINTE0L EPW7 EPW6 EPW5 EPW4 EPW3 EPW2 EPW1 EPW0 Interrupt request by PWC0 underflow: disabled Interrupt request by PWC0 underflow: enabled Interrupt request by PWC1 underflow: disabled Interrupt request by PWC1 underflow: enabled...
Page 240 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions PWINTE1L EPWR7 EPWR6 EPWR5 EPWR4 EPWR3 EPWR2 EPWR1 EPWR0 Interrupt request by match of PWC0 and PWR0 : disabled Interrupt request by match of PWC0 and PWR0 : enabled Interrupt request by match of PWC1 and PWR1 : disabled...
Page 241: Operation Of Pwm
MSM66591/ML66592 User's Manual Chapter 13 PWM Functions 13.2 Operation of PWM PWM0–PWM11 control duty within a specific cycle (determined by the count clock of PWC0–PWC11 or by the contents of PWC0–PWC11 and PWC0BF–PWC11BF). PWM is started by setting the corresponding RUN bit to "1". If the RUN bit becomes "1", the output F/F is set to "1"...
Page 242 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions The calculation of a PWM cycle is shown below. ¥ PWCLK ¥ : cycle of PWM (Hz) (PWM) (OSC) (PWM) N + 1 : master clock frequency (Hz) (OSC) PWCLK: input clock of PWM N: PWCn and PWCnBF value (n = 0–11)
Page 243 MSM66591/ML66592 User's Manual Chapter 13 PWM Functions Master clock (CLK) PWC clock: TBCCLK (dividing ratio of the 1/n counter: 1/4) Content of PWC 100H 0FFH 0FEH Match signal of PWC and PWR Change of PWM output pin MIS1 Figure 13-19 PWM Output Timing Change Example...
Page 244: Chapter 14 Baud Rate Generator Functions
Chapter 14 Baud Rate Generator Functions...
Page 246 Chapter 14 Baud Rate Generator Functions 14. Baud Rate Generator Functions The MSM66591/ML66592 have five serial communication functions: the UART serial ports 0, 2, 3, 4 and the synchronous/UART serial port 1. Each serial port has 8-bit timers (S0TM, S1TM, S2TM, S3TM, S4TM) that can be used as baud rate generators.
Page 247 MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions Table 14-1 S0TM, S1TM, S2TM, S3TM, S4TM Control SFRs Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0120 SCI0 Timer — S0TM 0000 0121 0122...
Page 248: Configuration Of Sci0 Timer (S0Tm)
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.1 Configuration of SCI0 Timer (S0TM) The SCI0 timer (S0TM) consists of an 8-bit SCI0 timer counter, an 8-bit SCI0 timer register that stores the reload values of the SCI0 timer counter, and a control register (S0CON) that specifies the timer counter operations.
Page 249 MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions • S0RUN (bit 4) This bit specifies the RUN/STOP of the SCI0 timer counter. If this bit is "0", the SCI0 timer counter stops, and if "1", it runs. • S0CK0–S0CK2 (bits 5–7) These three bits specify the count clock of the SCI0 timer counter.
Page 250: Operation Of Sci0 Timer
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.2 Operation of SCI0 Timer Basically the SCI0 timer operates as an auto reload timer. If the 8-bit SCI0 timer counter overflows, the value of the 8-bit SCI0 timer register is loaded to the counter. At the same time, an interrupt request by overflow is generated.
Page 251: Configuration Of Sci1 Timer (S1Tm)
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.3 Configuration of SCI1 Timer (S1TM) The SCI1 timer (S1TM) consists of an 8-bit SCI1 timer counter, an 8-bit SCI1 timer register that stores the reload values of the SCI1 timer counter, and a control register (S1CON) that specifies S1TM operations.
Page 252 MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions • S1RUN (bit 4) This bit specifies the RUN/STOP of the SCI1 timer counter. If this bit is "0", the SCI1 timer counter stops, and if "1", it runs. • S1CK0–S1CK2 (bits 5–7) These three bits specify the count clock of the SCI1 timer counter.
Page 253: Operation Of Sci1 Timer
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.4 Operation of SCI1 Timer Basically the SCI1 timer operates as the auto-reload timer. If the 8-bit timer counter (S1TM) overflows, the value of the 8-bit register (S1TMR) is loaded. At the same time, an interrupt request by an overflow is generated.
Page 254: Configuration Of Sci2 Timer (S2Tm)
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.5 Configuration of SCI2 Timer (S2TM) The SCI2 timer (S2TM) consists of an 8-bit SCI2 timer counter, an 8-bit SCI2 timer register that stores the reload values of the SCI2 timer counter, and a control register (S2CON) that specifies S2TM operations.
Page 255 MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions • S2RUN (bit 4) This bit specifies the RUN/STOP of the SCI2 timer counter. If this bit is "0", the SCI2 timer counter stops, and if "1", it runs. • S2CK0–S2CK2 (bits 5–7) These three bits specify the count clock of the SCI2 timer counter.
Page 256: Operation Of Sci2 Timer
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.6 Operation of SCI2 Timer Basically the SCI2 timer operates as an auto reload timer. If the 8-bit SCI2 timer counter overflows, the value of the 8-bit SCI2 timer register is loaded to the counter. At the same time, an interrupt request by overflow is generated.
Page 257: Configuration Of Sci3 Timer (S3Tm)
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.7 Configuration of SCI3 Timer (S3TM) The SCI3 timer (S3TM) consists of an 8-bit SCI3 timer counter, an 8-bit SCI3 timer register that stores the reload values of the SCI3 timer counter, and a control register (S3CON) that specifies S3TM operations.
Page 258 MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions • S3RUN (bit 4) This bit specifies the RUN/STOP of the SCI3 timer counter. If this bit is "0", the SCI3 timer counter stops, and if "1", it runs. • S3CK0–S3CK2 (bits 5–7) These three bits specify the count clock of the SCI3 timer counter.
Page 259: Operation Of Sci3 Timer
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.8 Operation of SCI3 Timer Basically the SCI3 timer operates as an auto reload timer. If the 8-bit SCI3 timer counter overflows, the value of the 8-bit SCI3 timer register is loaded to the counter. At the same time, an interrupt request by overflow is generated.
Page 260: Configuration Of Sci4 Timer (S4Tm)
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.9 Configuration of SCI4 Timer (S4TM) The SCI4 timer (S4TM) consists of an 8-bit SCI4 timer counter, an 8-bit SCI4 timer register that stores the reload values of the SCI4 timer counter, and a control register (S4CON) that specifies S4TM operations.
Page 261 MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions • S4RUN (bit 4) This bit specifies the RUN/STOP of the SCI4 timer counter. If this bit is "0", the SCI4 timer counter stops, and if "1", it runs. • S4CK0–S4CK2 (bits 5–7) These three bits specify the count clock of the SCI4 timer counter.
Page 262: Operation Of Sci4 Timer
MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14.10 Operation of SCI4 Timer Basically the SCI4 timer operates as an auto reload timer. If the 8-bit SCI4 timer counter overflows, the value of the 8-bit SCI4 timer register is loaded to the counter. At the same time, an interrupt request by overflow is generated.
Page 263 MSM66591/ML66592 User's Manual Chapter 14 Baud Rate Generator Functions 14-18...
Page 264: Chapter 15 Serial Port Functions
Chapter 15 Serial Port Functions...
Page 266 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15. Serial Port Functions The MSM66591/ML66592 have five channels of serial ports (SCI0, SCI1, SCI2, SCI3, SCI4). Each has a dedicated baud rate generator, and the communication speeds can be set independently.
Page 267: Configuration Of Serial Ports
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15.1 Configuration of Serial Ports SCI0, SCI1, SCI2, SCI3, and SCI4 have the same basic configuration. They consist of: • baud rate generators to control the transfer speed (S0TM, S1TM, S2TM, S3TM, S4TM: see Chapter 14) •...
Page 268 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions Table 15-2 Serial Port Control SFRs Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0026 S1BUF — Undefined SCI1 Transmit/Receive Buffer Register 0027 SCI1 Status Register S1STAT —...
Page 269 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions Table 15-2 Serial Port Control SFRs (continued) Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 0190 SCI0 Status Register 1 S0STAT1 — 0191 SCI0 Status Register 2 S0STAT2 —...
Page 270: Serial Port Control Registers
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15.2 Serial Port Control Registers 15.2.1 Control Registers for SCI0 SCI0 Transmit Control Register (ST0CON) ST0CON is a 5-bit register that controls SCI0 transmit operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog...
Page 271 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions ST0CON — ST0EVN ST0PEN ST0STB — ST0MPC — ST0MD 0 SCI0 UART normal mode SCI0 UART multiprocessor communication mode Multiprocessor communication 0 Data transmitted mode 1 Address transmitted 0 2 stop bits...
Page 272: Sci0 Receive Control Register (Sr0Con)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI0 Receive Control Register (SR0CON) SR0CON is a 5-bit register that controls SCI0 receive operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SR0CON becomes 12H, the SCI0 operation is in UART normal mode, at 8-bit data length, no parity, and receive is disabled.
Page 273 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SR0CON SR0REN SR0EVN SR0PEN — SR0EXP SR0MPC — SR0MD 0 SCI0 UART normal mode SCI0 UART multiprocessor communication mode Multiprocessor communication 0 Data is received mode 1 Address is received 0 Single buffer mode...
Page 274: Sci0 Transmit/Receive Buffer Register (S0Buf0)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI0 Transmit/Receive Buffer Register (S0BUF0) S0BUF0 is an 8-bit register that holds transmit/receive data during a serial port transmit/ receive operation. S0BUF0 has a double structure, in which the contents are different in read/write.
Page 275: Sci0 Status Register 0 (S0Stat0)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI0 Status Register 0 (S0STAT0) The high-order 4 bits of S0STAT0 is the transmit-ready/receive-ready interrupt request control register of the serial port. The low-order 4 bits of S0STAT0 is the register that holds the status (normal/abnormal) when the serial port receive operation is completed.
Page 276 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Description of Each Bit> • FERR0 (bit 0) If the stop bit received by SCI0 is "0", this bit is set to "1" interpreting that frame synchronization is incorrect. (Framing error) • OERR00 (bit 1) This bit is set to "1"...
Page 277 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions S0STAT0 TR0IRQ TR0IE RV0IRQ0 RV0IE0 MERR00 PERR00 OERR00 FERR0 SCI0 framing error:no SCI0 framing error:yes S0BUF0 overrun error:no S0BUF0 overrun error:yes S0BUF0 parity error:no S0BUF0 parity error:yes S0BUF0 multiprocessor communication error:no S0BUF0 multiprocessor communication error:yes...
Page 278: Sci0 Status Register 1 (S0Stat1)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI0 Status Register 1 (S0STAT1) If the SR0EXP bit of SR0CON is set to "1" (4-stage buffer mode), the 6-bit S0STAT1 register stores the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 279 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions • PERR02 (bit 6) With SCI0, the parity of data received by S0BUF2 is compared to the parity bit appended to and transferred with the data. If they do not match, PERR02 is set to "1".
Page 280: Sci0 Status Register 2 (S0Stat2)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI0 Status Register 2 (S0STAT2) If the SR0EXP bit of SR0CON is set to "1" (4-stage buffer mode), the lower 3 bits of S0STAT2 store the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 281 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions S0STAT2 — — MERR03 PERR03 OERR03 — BFCU01 BFCU00 S0BUF3 overrun error: no S0BUF3 overrun error: yes S0BUF3 parity error: no S0BUF3 parity error: yes S0BUF3 multiprocessor communication error: no S0BUF3 multiprocessor communication error: yes...
Page 282: Sci0 Interrupt Control Register (Sr0Int)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI0 Interrupt Control Register (SR0INT) When SCI0 is in the 4-stage buffer mode (SR0EXP bit of SR0CON is "1"), the 7-bit SR0INT register controls the receive-ready interrupt requests for each receive buffer (S0BUF0 to S0BUF3).
Page 283 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SR0INT RV0IRQ3 RV0IRQ1 RV0IE3 RV0IE2 RV0IE1 — RV0IRQ2 RV0IRQ0 S0BUF1 receive-ready interrupt request generation: disabled S0BUF1 receive-ready interrupt request generation: enabled S0BUF2 receive-ready interrupt request generation: disabled S0BUF2 receive-ready interrupt request generation: enabled...
Page 284: Control Registers For Sci1
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15.2.2 Control Registers for SCI1 SCI1 Transmit Control Register (ST1CON) ST1CON is a 6-bit register that controls SCI1 transmit operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog...
Page 285 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions ST1CON ST1STB — ST1EVN ST1PEN — ST1MPC ST1MD1 ST1MD0 ST1MST ST1MD SCI1 Transmit Operation Mode UART normal mode UART multiprocessor communication mode Synchronous normal mode Synchronous multiprocessor communication mode Multiprocessor communication 0 Data transmit...
Page 286: Sci1 Receive Control Register (Sr1Con)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI1 Receive Control Register (SR1CON) SR1CON is 7-bit register that controls the SCI1 receive operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SR1CON becomes 08H, the SCI1 receive operation is in UART normal mode, at 8-bit data length, no parity, and receive is disabled.
Page 287 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SR1CON SR1REN SR1EVN SR1PEN SR1MST — SR1MPC SR1MD1 SR1MD0 SR1MD SCI1 Receive Operation Mode UART normal mode UART multi-processor communication mode Synchronous normal mode Synchronous multiprocessor communication mode Multiprocessor communication 0 Data receive...
Page 288: Sci1 Transmit/Receive Buffer Register (S1Buf)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI1 Transmit/Receive Buffer Register (S1BUF) S1BUF is an 8-bit register that holds transmit/receive data during a serial port transmit/ receive operation. S1BUF has a double structure, in which the content is different in READ/WRITE.
Page 289 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Description of Each Bit> • FERR1 (bit 0) If the stop bit received by SCI1 is "0", this bit is set to "1" interpreting that frame synchronization is incorrect. (Framming error) • OERR1 (bit 1) This bit is set to "1"...
Page 290 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions S1STAT TR1IRQ TR1IE RV1IRQ RV1IE MERR1 PERR1 OERR1 FERR1 0 SCI1 framing error:no 1 SCI1 framing error:yes 0 SCI1 overrun error:no 1 SCI1 overrun error:yes 0 SCI1 parity error:no 1 SCI1 parity error:yes...
Page 291: Control Registers For Sci2
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15.2.3 Control Registers for SCI2 SCI2 Transmit Control Register (ST2CON) ST2CON is a 5-bit register that controls SCI2 transmit operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog...
Page 292 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions ST2CON — ST2EVN ST2PEN ST2STB — ST2MPC — ST2MD 0 SCI2 UART normal mode SCI2 UART multiprocessor communication mode Multiprocessor communication 0 Data transmitted mode 1 Address transmitted 0 2 stop bits...
Page 293: Sci2 Receive Control Register (Sr2Con)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI2 Receive Control Register (SR2CON) SR2CON is a 5-bit register that controls SCI2 receive operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SR2CON becomes 12H, the SCI2 operation is in UART normal mode, at 8-bit data length, no parity, and receive is disabled.
Page 294 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SR2CON SR2REN SR2EVN SR2PEN — SR2EXP SR2MPC — SR2MD 0 SCI2 UART normal mode SCI2 UART multiprocessor communication mode Multiprocessor communication 0 Data is received mode 1 Address is received 0 Single buffer mode...
Page 295: Sci2 Transmit/Receive Buffer Register (S2Buf0)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI2 Transmit/Receive Buffer Register (S2BUF0) S2BUF0 is an 8-bit register that holds transmit/receive data during a serial port transmit/ receive operation. S2BUF0 has a double structure, in which the contents are different in read/write.
Page 296: Sci2 Status Register 0 (S2Stat0)
MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SCI2 Status Register 0 (S2STAT0) The high-order 4 bits of S2STAT0 is the transmit-ready/receive-ready interrupt request control register of the serial port. The low-order 4 bits of S2STAT0 is the register that holds the status (normal/abnormal) when the serial port receive operation is completed.
Page 297 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Description of Each Bit> • FERR2 (bit 0) If the stop bit received by SCI2 is "0", this bit is set to "1" interpreting that frame synchronization is incorrect. (Framing error) • OERR20 (bit 1) This bit is set to "1"...
Page 298 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions S2STAT0 TR2IRQ TR2IE RV2IRQ0 RV2IE0 MERR20 PERR20 OERR20 FERR2 SCI2 framing error:no SCI2 framing error:yes S2BUF0 overrun error:no S2BUF0 overrun error:yes S2BUF0 parity error:no S2BUF0 parity error:yes S2BUF0 multiprocessor communication error:no S2BUF0 multiprocessor communication error:yes...
Page 299: Sci2 Status Register 1 (S2Stat1)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI2 Status Register 1 (S2STAT1) If the SR2EXP bit of SR2CON is set to "1" (4-stage buffer mode), the 6-bit S2STAT1 register stores the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 300 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions • PERR22 (bit 6) With SCI2, the parity of data received by S2BUF2 is compared to the parity bit appended to and transferred with the data. If they do not match, PERR22 is set to "1".
Page 301: Sci2 Status Register 2 (S2Stat2)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI2 Status Register 2 (S2STAT2) If the SR2EXP bit of SR2CON is set to "1" (4-stage buffer mode), the lower 3 bits of S2STAT2 store the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 302 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions S2STAT2 — — BFCU21 MERR23 PERR23 OERR23 — BFCU20 S2BUF3 overrun error: no S2BUF3 overrun error: yes S2BUF3 parity error: no S2BUF3 parity error: yes S2BUF3 multiprocessor communication error: no S2BUF3 multiprocessor communication error: yes...
Page 303: Sci2 Interrupt Control Register (Sr2Int)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI2 Interrupt Control Register (SR2INT) When SCI2 is in the 4-stage buffer mode (SR2EXP bit of SR2CON is "1"), the 7-bit SR2INT register controls the receive-ready interrupt requests for each receive buffer (S2BUF0 to S2BUF3).
Page 304 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SR2INT RV2IRQ3 RV2IRQ2 RV2IRQ1 RV2IRQ0 RV2IE3 RV2IE2 RV2IE1 — S2BUF1 receive-ready interrupt request generation: disabled S2BUF1 receive-ready interrupt request generation: enabled S2BUF2 receive-ready interrupt request generation: disabled S2BUF2 receive-ready interrupt request generation: enabled...
Page 305: Control Registers For Sci3
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15.2.4 Control Registers for SCI3 SCI3 Transmit Control Register (ST3CON) ST3CON is a 5-bit register that controls SCI3 transmit operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog...
Page 306 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions ST3CON — ST3EVN ST3PEN ST3STB — ST3MPC — ST3MD 0 SCI3 UART normal mode SCI3 UART multiprocessor communication mode Multiprocessor communication 0 Data transmitted mode 1 Address transmitted 0 2 stop bits...
Page 307: Sci3 Receive Control Register (Sr3Con)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI3 Receive Control Register (SR3CON) SR3CON is a 5-bit register that controls SCI3 receive operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SR3CON becomes 12H, the SCI3 operation is in UART normal, single buffer mode, at 8-bit data length, no parity, and receive is disabled.
Page 308 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SR3CON SR3REN SR3EVN SR3PEN — SR3EXP SR3MPC — SR3MD 0 SCI3 UART normal mode SCI3 UART multiprocessor communication mode Multiprocessor communication 0 Data is received mode 1 Address is received 0 Single buffer mode...
Page 309: Sci3 Transmit/Receive Buffer Register (S3Buf0)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI3 Transmit/Receive Buffer Register (S3BUF0) S3BUF0 is an 8-bit register that holds transmit/receive data during a serial port trans- mit/receive operation. S3BUF0 has a double structure, in which the contents are different in read/write. If in read, S3BUF0 functions as a receive buffer, and if in write, S3BUF0 functions as a transmit buffer.
Page 310: Sci3 Status Register 0 (S3Stat0)
MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SCI3 Status Register 0 (S3STAT0) The high-order 4 bits of S3STAT0 is the transmit-ready/receive-ready interrupt request control register of the serial port. The low-order 4 bits of S3STAT0 is the register that holds the status (normal/abnormal) when the serial port receive operation is completed.
Page 311 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Description of Each Bit> • FERR3 (bit 0) If the stop bit received by SCI3 is "0", this bit is set to "1" interpreting that frame synchronization is incorrect. (Framing error) • OERR30 (bit 1) This bit is set to "1"...
Page 312 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions S3STAT0 TR3IRQ TR3IE RV3IRQ0 RV3IE0 MERR30 PERR30 OERR30 FERR3 SCI3 framing error:no SCI3 framing error:yes S3BUF0 overrun error:no S3BUF0 overrun error:yes S3BUF0 parity error:no S3BUF0 parity error:yes S3BUF0 multiprocessor communication error:no S3BUF0 multiprocessor communication error:yes...
Page 313: Sci3 Status Register 1 (S3Stat1)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI3 Status Register 1 (S3STAT1) If the SR3EXP bit of SR3CON is set to "1" (4-stage buffer mode), the 6-bit S3STAT1 register stores the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 314 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions • PERR32 (bit 6) With SCI3, the parity of data received by S3BUF2 is compared to the parity bit appended to and transferred with the data. If they do not match, PERR32 is set to "1".
Page 315: Sci3 Status Register 2 (S3Stat2)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI3 Status Register 2 (S3STAT2) If the SR3EXP bit of SR3CON is set to "1" (4-stage buffer mode), the lower 3 bits of S3STAT2 store the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 316 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions S3STAT2 — — BFCU31 BFCU30 MERR33 PERR33 OERR33 — S3BUF3 overrun error: no S3BUF3 overrun error: yes S3BUF3 parity error: no S3BUF3 parity error: yes S3BUF3 multiprocessor communication error: no S3BUF3 multiprocessor communication error: yes...
Page 317: Sci3 Interrupt Control Register (Sr3Int)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI3 Interrupt Control Register (SR3INT) When SCI3 is in the 4-stage buffer mode (SR3EXP bit of SR3CON is "1"), the 7-bit SR3INT register controls the receive-ready interrupt requests for each receive buffer (S3BUF0 to S3BUF3).
Page 318 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SR3INT RV3IRQ3 RV3IRQ1 RV3IE3 RV3IE2 RV3IE1 — RV3IRQ2 RV3IRQ0 S3BUF1 receive-ready interrupt request generation: disabled S3BUF1 receive-ready interrupt request generation: enabled S3BUF2 receive-ready interrupt request generation: disabled S3BUF2 receive-ready interrupt request generation: enabled...
Page 319: Control Registers For Sci4
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15.2.5 Control Registers for SCI4 SCI4 Transmit Control Register (ST4CON) ST4CON is a 5-bit register that controls SCI4 transmit operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog...
Page 320 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions ST4CON — ST4EVN ST4PEN ST4STB — ST4MPC — ST4MD 0 SCI4 UART normal mode SCI4 UART multiprocessor communication mode Multiprocessor communication 0 Data is transmitted mode 1 Address is transmitted 0 2 stop bits...
Page 321: Sci4 Receive Control Register (Sr4Con)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI4 Receive Control Register (SR4CON) SR4CON is a 5-bit register that controls SCI4 receive operations. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SR4CON becomes 12H, the SCI4 operation is in UART normal, single buffer mode, at 8-bit data length, no parity, and receive is disabled.
Page 322 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SR4CON SR4REN SR4EVN SR4PEN — SR4EXP SR4MPC — SR4MD 0 SCI4 UART normal mode SCI4 UART multiprocessor communication mode Multiprocessor communication 0 Data is received mode 1 Address is received 0 Single buffer mode...
Page 323: Sci4 Transmit/Receive Buffer Register (S4Buf0)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI4 Transmit/Receive Buffer Register (S4BUF0) S4BUF0 is an 8-bit register that holds transmit/receive data during a serial port trans- mit/receive operation. S4BUF0 has a double structure, in which the contents are different in read/write. If in read, S4BUF0 functions as a receive buffer, and if in write, S4BUF0 functions as a transmit buffer.
Page 324: Sci4 Status Register 0 (S4Stat0)
MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SCI4 Status Register 0 (S4STAT0) The high-order 4 bits of S4STAT0 is the transmit-ready/receive-ready interrupt request control register of the serial port. The low-order 4 bits of S4STAT0 is the register that holds the status (normal/abnormal) when the serial port receive operation is completed.
Page 325 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Description of Each Bit> • FERR4 (bit 0) If the stop bit received by SCI4 is "0", this bit is set to "1" interpreting that frame synchronization is incorrect. (Framing error) • OERR40 (bit 1) This bit is set to "1"...
Page 326 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions S4STAT0 TR4IRQ TR4IE RV4IRQ0 RV4IE0 MERR40 PERR40 OERR40 FERR4 SCI4 framing error:no SCI4 framing error:yes S4BUF0 overrun error:no S4BUF0 overrun error:yes S4BUF0 parity error:no S4BUF0 parity error:yes S4BUF0 multiprocessor communication error:no S4BUF0 multiprocessor communication error:yes...
Page 327: Sci4 Status Register 1 (S4Stat1)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI4 Status Register 1 (S4STAT1) If the SR4EXP bit of SR4CON is set to "1" (4-stage buffer mode), the 6-bit S4STAT1 register stores the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 328 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions • PERR42 (bit 6) With SCI4, the parity of data received by S4BUF2 is compared to the parity bit appended to and transferred with the data. If they do not match, PERR42 is set to "1".
Page 329: Sci4 Status Register 2 (S4Stat2)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI4 Status Register 2 (S4STAT2) If the SR4EXP bit of SR4CON is set to "1" (4-stage buffer mode), the lower 3 bits of S4STAT2 store the status (normal/abnormal) of the serial transfer when a serial port receive operation is completed.
Page 330 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions S4STAT2 — — BFCU41 MERR43 PERR43 OERR43 — BFCU40 S4BUF3 overrun error: no S4BUF3 overrun error: yes S4BUF3 parity error: no S4BUF3 parity error: yes S4BUF3 multiprocessor communication error: no S4BUF3 multiprocessor communication error: yes...
Page 331: Sci4 Interrupt Control Register (Sr4Int)
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions SCI4 Interrupt Control Register (SR4INT) When SCI4 is in the 4-stage buffer mode (SR4EXP bit of SR4CON is "1"), the 7-bit SR4INT register controls the receive-ready interrupt requests for each receive buffer (S4BUF0 to S4BUF3).
Page 332 MSM66591/ML66952 User's Manual Chapter 15 Serial Port Functions SR4INT RV4IRQ3 RV4IRQ2 RV4IRQ1 RV4IRQ0 RV4IE3 RV4IE2 RV4IE1 — S4BUF1 receive-ready interrupt request generation: disabled S4BUF1 receive-ready interrupt request generation: enabled S4BUF2 receive-ready interrupt request generation: disabled S4BUF2 receive-ready interrupt request generation: enabled...
Page 333: Operation Of Serial Ports
STnCON, and a stop bit is finally added, and a 1 frame transmission ends. In the MSM66591/ML66592 serial port transmit circuit, SnBUF0 and the transmit register have a double structure, so that the next data can be written to SnBUF0 during a transmission.
Page 334 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-69...
Page 335 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Synchronous Normal Master Mode (SCI1 only)> The clock pulse (BRG1), generated by the baud rate generator (S1TM), is divided by 4 to generate the transmit shift clock (ST1CLK) (refer to Figure 15-31).
Page 336 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-71...
Page 337 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Synchronous Normal Slave Mode (SCI1 only)> In slave mode, the transmit clock is input externally. The edge is detected synchronizing with a CLK to generate ST1CLK (refer to Figure 15-32). The transmit circuit controls the transfer of the transmit data synchronizing with ST1CLK.
Page 338 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-73...
Page 339: Receive Operation
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15.3.2 Receive Operation The UART mode used by the SCI0, SCI2, SCI3, and SCI4 serial ports on the receive side has a single buffer mode and a 4-stage buffer mode. Single buffer mode has a single stage of receive buffer, and 4-stage buffer mode has four stages of receive buffers.
Page 340 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-75...
Page 341 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Synchronous Normal Master Mode (SCI1 only)> The clock pulse (BRG1), generated by the baud rate generator (S1TM), is divided by 4 to generate the receive shift clock (SR1CLK), and the receive data sampling clock is generated (refer to Figure 15-34).
Page 342 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-77...
Page 343 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions <Synchronous Normal Slave Mode (SCI1 only)> The receive operation starts when SR1REN of SR1CON is set to "1" by the program. SR1FREE, that indicates receiving, becomes "L" level, and the receive shift clock to input to the RXC1 pin is accepted (refer to Figure 15-35).
Page 344 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-79...
Page 345 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-80...
Page 346: 4-Stage Buffer Mode
MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 4-Stage Buffer Mode The 4-stage buffer mode is entered by setting SRnEXP (bit 3) of SRnCON. During the 4-stage buffer mode, consecutive reception of up to a maximum of 4 bytes is possible.
Page 347 MSM66591/ML66592 User's Manual Chapter 15 Serial Port Functions 15-82...
Page 348: Chapter 16 A/D Converter Functions
Chapter 16 A/D Converter Functions...
Page 350 Chapter 16 A/D Converter Functions 16. A/D Converter Functions The MSM66591/ML66592 have two sets of 10-bit A/D converters that support 12 channels of analog input, A/D Converter 0 (ADC0) and A/D Converter 1 (ADC1). The basic configuration of A/D converter 0 and A/D converter 1 is the same, with the only difference being the address of registers located in the SFR area.
Page 351 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADCR0 ADCR1 ADCR2 Conversion Circuit ADCR3 ADCR4 AGND ADCR5 ADCR6 ADCR7 ADCR8 Interrupt Analog ADCR9 Request Selector ADCR10 Selector ADCR11 AI11 ADCON0L ADHSCON ADCON0H ADHENCON ADINTCON0 ADHSEL0 Internal Bus Figure 16-1 Configuration of A/D Converter 0 (ADC0) For A/D converter specifications, see Chapter 25, "Electrical Characteristics."...
Page 352 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions Table 16-1 A/D Converter Contol SFR List Abbreviated Abbreviated 8/16-Bit Reset Address [H] Name Name (BYTE) Name (WORD) Operation State [H] 00E0 A/D Result Register 0 — ADCR0 Undefined 00E1 A/D Result Register 1 —...
Page 353: Configuration Of A/D Converter
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions 16.1 Configuration of A/D Converter Since the basic configurations of the A/D converter 0 and the A/D converter 1 are the same, this section chiefly explains the configuration of A/D converter 0.
Page 354 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions The A/D hard select mode is controlled by the A/D hard select register 0 (ADHSEL0), A/ D hard select register 1 (ADHSEL1), and A/D hard select enable register (ADHENCON). An interrupt source to activate the A/D hard select mode is set to each channel (ch0–...
Page 355 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions If a higher priority mode A/D conversion request is generated while a lower priority mode A/D conversion is being performed, the ongoing A/D conversion is suspended and restarts after completion of the requested convension.
Page 356: Control Register Of A/D Converter
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions 16.2 Control Register of A/D Converter A/D Control Register 0L (ADCON0L) ADCON0L is a 7-bit register that primarily controls the scan mode of the A/D converter. Figure 16-5 shows the configuration of ADCON0L.
Page 357 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions • SCNC0 (bit 6) This bit specifies the operation after a scan channel cycle is completed. If this bit is "0", A/D conversion starts from the first channel again, after a scan channel cycle is completed.
Page 358: A/D Control Register 1L (Adcon1L)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Control Register 1L (ADCON1L) ADCON1L is a 7-bit register that primarily controls the scan mode of the A/D converter. Figure 16-6 shows the configuration of ADCON1L. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), ADCON1L becomes 80H.
Page 359 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions • SCNC1 (bit 6) This bit specifies the operation after a scan channel cycle is completed. If this bit is "0", A/D conversion starts from the first channel again, after a scan channel cycle is completed.
Page 360: A/D Control Register 0H (Adcon0H)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Control Register 0H (ADCON0H) The ADCON0H is a 7-bit register that primarily controls the select mode of the A/D converter 0. Figure 16-7 shows the configuration of ADCON0H. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), ADCON0H becomes 80H.
Page 361 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADCON0H — ADTM01 ADTM00 STS0 ADSTM03 ADSTM02 ADSTM01 ADSTM00 ADSTM0 A/D Converter 0 Select Channel 3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1...
Page 362: A/D Control Register 1H (Adcon1H)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Control Register 1H (ADCON1H) The ADCON1H is a 7-bit register that primarily controls the select mode of the A/D converter 1. Figure 16-8 shows the configuration of ADCON1H. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), ADCON1H becomes 80H.
Page 363 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADCON1H — ADTM11 ADTM10 STS1 ADSTM13 ADSTM12 ADSTM11 ADSTM10 ADSTM1 A/D Converter 1 Select Channel 3 2 1 0 0 0 0 0 ch12 0 0 0 1 ch13 0 0 1 0...
Page 364: A/D Interrupt Control Register 0 (Adintcon0)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Interrupt Control Register 0 (ADINTCON0) ADINTCON0 is a 6-bit register that primarily controls the interrupt request generation of the A/D converter 0. Figure 16-9 shows the configuration of ADINTCON0. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), ADINTCON0 becomes C0H.
Page 365 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADINTCON0 — — INTHS0 ADSTIE0ADSNIE0 INTST0 INTSN0 ADHSIE0 Scan channel cycle: no Scan channel cycle: yes Select mode end: no Select mode end: yes Interrupt request generation by INTSN0: disabled Interrupt request generation by INTSN0: enabled...
Page 366: A/D Interrupt Control Register 1 (Adintcon1)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Interrupt Control Register 1 (ADINTCON1) ADINTCON1 is a 6-bit register that primarily controls the interrupt request generation of the A/D converter 1. Figure 16-10 shows the configuration of ADINTCON1. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), ADINTCON1 becomes C0H.
Page 367 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADINTCON1 — — INTHS1 ADSTIE1ADSNIE1 INTST1 INTSN1 ADHSIE1 Scan channel cycle: no Scan channel cycle: yes Select mode end: no Select mode end: yes Interrupt request generation by INTSN1: disabled Interrupt request generation by INTSN1: enabled...
Page 368: A/D Hard Select Register 0 (Adhsel0)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Hard Select Register 0 (ADHSEL0) The ADHSEL0 register is used to set an interrupt cause to activate the hard select mode of A/D converter 0 to individual channels. Channel 0, channel 1, channel 2, and channel 3 each have 4 bits (total of 16 bits).
Page 369 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADHSEL0 A/D Hard Select Mode Activation 3 2 1 Interrupt Cause to Channel 0 0 0 0 PWC0/PWC1 underflow or match 0 0 0 PWC2/PWC3 underflow or match 0 0 1 PWC4/PWC5 underflow or match...
Page 370 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADHSEL0 (bits 8–15) A/D Hard Select Mode Activation 11 10 9 Interrupt Cause to Channel 2 0 0 0 PWC0/PWC1 underflow or match 0 0 0 PWC2/PWC3 underflow or match 0 0 1...
Page 371: A/D Hard Select Register 1 (Adhsel1)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Hard Select Register 1 (ADHSEL1) The ADHSEL1 register is used to set an interrupt cause to activate the hard select mode of A/D converter 1 to individual channels. Channel 12, channel 13, channel 14, and channel 15 each have 4 bits (total of 16 bits).
Page 372 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADHSEL1 (bits 0–7) A/D Hard Select Mode Activation 3 2 1 Interrupt Cause to Channel 12 0 0 0 PWC0/PWC1 underflow or match 0 0 0 PWC2/PWC3 underflow or match 0 0 1...
Page 373 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADHSEL1 (bits 8–15) A/D Hard Select Mode Activation 11 10 9 Interrupt Cause to Channel 14 0 0 0 PWC0/PWC1 underflow or match 0 0 0 PWC2/PWC3 underflow or match 0 0 1...
Page 374: A/D Hard Select Software-Control Register (Adhscon)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions A/D Hard Select Software-Control Register (ADHSCON) ADHSCON is a 2-bit register that activates, through software, A/D conversion in the A/ D hard select mode. Writing a "1" to bit 1 or bit 0 of ADHSCON starts A/D conversion in the A/D hard select mode.
Page 375: A/D Hard Select Enable Register (Adhencon)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions [10] A/D Hard Select Enable Register (ADHENCON) ADHENCON is an 8-bit register that controls enable/disable of the hard select mode for each channel (ch0, ch1, ch2, ch3, ch12, ch13, ch14, ch15). Figure 16-16 shows the configuration of ADHENCON.
Page 376 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions ADHENCON ADHENC3 ADHENC2 ADHENC1 ADHENC0 ADHENC15 ADHENC14 ADHENC13 ADHENC12 ch0 hard select mode: disabled ch0 hard select mode: enabled ch1 hard select mode: disabled ch1 hard select mode: enabled ch2 hard select mode: disabled...
Page 377: A/D Result Registers (Adcr0-Adcr23)
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions [11] A/D Result Registers (ADCR0–ADCR23) The A/D result registers are 16-bit registers that store A/D conversion results. Conver- sion results are stored in the upper 10 bits (bit 15–bit 6) of the A/D result registers.
Page 378: Generated Timing Of The A/D Hard Select Mode
MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions 16.3 Generated Timing of the A/D Hard Select Mode A/D conversion in the A/D hard select mode is activated 1 CLK after the interrupt request flag (IRQF) is set in synchronization with the first M1S1 signal following the generation of any peripheral event (matching, overflow, etc.).
Page 379 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions Activation of Hard Select Mode A/D Conversion during Select Mode Operation When the valid edge for the hard select mode occurs during select mode operation, the select mode is suspended and 1 clock after the first M1S1 signal following generation of the activation request, A/D conversion in the hard select mode is activated.
Page 380 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions Hard Select Mode Contention a) ch1 (low priority) request is generated after ch0 (high priority) activation When a low priority hard select mode activation request is generated during A/D conversion in a high priority hard select mode, the request is placed on hold. A/D conversion in the low priority hard select mode will begin 1 clock after the A/D conver- sion in the high priority hard select mode is completed.
Page 381 MSM66591/ML66592 User's Manual Chapter 16 A/D Converter Functions 16-32...
Page 382: Chapter 17 Transition Detector Functions
Chapter 17 Transition Detector Functions...
Page 384: Transition Detector Control Register (Trnscon)
Chapter 17 Transition Detector Functions 17. Transition Detector Functions The MSM66591/ML66592 have eight transition detector functions, which detect the valid edges (rise, fall, both edges) of an input pin. If the valid edge specified by TRNSCON is input to TRNS0–TRNS7 pins, the corre- sponding bit 0 to bit 7 of the transition detector (TRNSIT) is set to "1".
Page 385 MSM66591/ML66592 User's Manual Chapter 17 Transition Detector Functions TRNSCON (bits 0–7) Valid edge of TRNS0 Falling edge Rising edge Both edges Valid edge of TRNS1 Falling edge Rising edge Both edges Valid edge of TRNS2 Falling edge Rising edge Both edges...
Page 386: Transition Detector Register (Trnsit)
MSM66591/ML66592 User's Manual Chapter 17 Transition Detector Functions 17.2 Transition Detector Register (TRNSIT) TRNSIT is an 8-bit register that indicates that the valid edge specified by TRNSCON has been input to a TRNS pin. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), TRNSIT becomes 00H.
Page 387 MSM66591/ML66592 User's Manual Chapter 17 Transition Detector Functions 17-4...
Page 388: Chapter 18 Peripheral Functions
Chapter 18 Peripheral Functions...
Page 390: Clockout Function
MSM66591/ML66592 User's Manual Chapter 18 Peripheral Functions 18. Peripheral Functions The MSM66591/ML66592 have the following three functions for use in a peripheral IC. A. clockout function B. RES pin valid level detection function C. OE pin monitor function 18.1 Clockout Function The clockout function outputs the divided master clock of the MSM66591/ML66592 from the CLKOUT pin (secondary function of P5_6).
Page 391 CKOUT CLKOUT Pin Output Clock 1/2 CLK 1/4 CLK 1/8 CLK 1/16 CLK 2/3 CLK (MSM66591 only) 1/3 CLK RES pin did not become "L" level RES pin became "L" level OE pin "L" level OE pin "H" level "—" indicates a bit that is not provided.
Page 392: Chapter 19 External Interrupt Request Function
Chapter 19 External Interrupt Request Function...
Page 394 Chapter 19 External Interrupt Request Function 19. External Interrupt Request Function The MSM66591/ML66592 have four inputs for external interrupt requests, which can be classified into two types. One type is a maskable interrupt, and there are three (INT0, INT1, INT2). The other type is a nonmaskable interrupt, and there is one (NMI).
Page 395 MSM66591/ML66592 User's Manual Chapter 19 External Interrupt Request Function EXICON — — EX2M1 EX2M0 EX1M1 EX1M0 EX0M1 EX0M0 EX0M Valid Edge of INT0 "L" level Falling edge Rising edge Both edges EX1M Valid Edge of INT1 "L" level Falling edge...
Page 396: Chapter 20 Interrupt Request Processing Function
Chapter 20 Interrupt Request Processing Function...
Page 398 Chapter 20 Interrupt Request Processing Function 20. Interrupt Request Processing Function The MSM66591/ML66592 have 67 types of interrupt causes (external 4, internal 63), which are assigned to 39 vectors. One external interrupt is nonmaskable. Also four levels of interrupt priorities can be set for maskable interrupts.
Page 399: Non-Maskable Interrupt (Nmi)
Fourteen cycle are required to shift to each of these NMI process. However, if the program memory space is extended to 128K bytes (MSM66591) or 192K bytes (ML66592) by setting bit 1 (LROM) of MEMSCON to "1", 17 cycles are required be- cause cycles required to save the code segment register (CSR) are added.
Page 400 MSM66591/ML66592 User's Manual Chapter 20 Interrupt Request Processing Function [Note] If the program memory space is extended to 128K bytes (MSM66591) or 192K bytes (ML66592) by setting bit 1 (LROM) of MEMSCON to "1", the code segment register (CSR), in addition to the above registers, is saved and restored.
Page 401: Maskable Interrupt
MSM66591/ML66592 User's Manual Chapter 20 Interrupt Request Processing Function 20.2 Maskable Interrupt A maskable interrupt is generated by various causes such as internal peripheral hardware and external pin inputs. A maskable interrupt is controlled by: q Register (IRQD) that enables/disables IRQ flag to be set to "1" by the interrupt request generated by each factor.
Page 402 MSM66591/ML66592 User's Manual Chapter 20 Interrupt Request Processing Function Table 20-2 Vector Addresses and Bit Symbols for Maskable Interrupts Vector Interrupt Cause IRQD IPX0 IPX1 Address [H] External interrupt 0 (INT0) 000A DINT0 QINT0 EINT0 P0INT0 P1INT0 TM0 overflow 000C...
Page 403: Interrupt Request Flag Disable Register Irqd
MSM66591/ML66592 User's Manual Chapter 20 Interrupt Request Processing Function Interrupt Request Flag Disable Register IRQD (IRQD0L, IRQD0H, IRQD1L, IRQD1H, IRQD2L) The IRQD is a register that enables/disables the corresponding bit of the IRQ to be set to "1" by the interrupt signal from each interrupt generation source. If a bit of IRQD is "1", the corresponding bit of IRQ is not set, even if the corresponding interrupt genera-...
Page 404: Interrupt Priority Control Register
MSM66591/ML66592 User's Manual Chapter 20 Interrupt Request Processing Function Interrupt Priority Control Register IPX0 (IP00L, IP00H, IP10L, IP10H, IP20L), IPX1 (IP01L, IP01H, IP11L, IP11H, IP21L) As a pair IPX0 and IPX1 specify the priority of maskable interrupts. If the corresponding bit of IPX0 and IPX1 for a maskable interrupt is PX0xxx and PX1xxx, the priority given to the maskable interrupt is as follows.
Page 405: Operation Of Maskable Interrupt
MSM66591/ML66592 User's Manual Chapter 20 Interrupt Request Processing Function 20.3 Operation of Maskable Interrupt When an interrupt request signal is generated, the logic to notify about interrupt request generation to the judgment logic of an interrupt priority functions as follows: •...
Page 406 • Restoring program counter (PC) and then ending the maskable interrupt routine. [Note] If the program memory space is expanded to 128K bytes (MSM66591) or 192K bytes (ML66592) by setting bit 1 (LROM) of MEMSCON to "1", the code segment register (CSR) is saved or returned from.
Page 407 MSM66591/ML66592 User's Manual Chapter 20 Interrupt Request Processing Function 20-10...
Page 408: Chapter 21 Bus Port Functions
Chapter 21 Bus Port Functions...
Page 410: Access
MSM66591/ML66592 User's Manual Chapter 21 Bus Port Functions 21. Bus Port Functions The MSM66591/ML66592 can externally expand up to 128K bytes (MSM66591) or 256K bytes (ML66592) of program memory (ROM usually) by setting the EA pin to a "L" level.
Page 411: External Memory Access
21.2.2 External Program Memory Access Timing Figures 21-2 and 21-3 show external program memory access timing. The MSM66591/ML66592 have a function to insert a wait cycle when the external memory access time is slow. (READY function: see 5.2). Use this function according to the access time of the external memory required for use.
Page 412 MSM66591/ML66592 User's Manual Chapter 21 Bus Port Functions P7_2/ALE P7_3/PSEN AD0–AD7 PC0–7 INST0–7 PC0–7 INST0–7 (P0_0–P0_7) A8–A16 PC8–16 PC8–16 (P1_0–P1_7, P12_0) [Note] 1 wait cycle is automatically inserted into the CPU in this case as well. In the ML66592, the timing for A17 (address 17) is the same as A8–A16.
Page 413 MSM66591/ML66592 User's Manual Chapter 21 Bus Port Functions 21-4...
Page 414: Chapter 22 Expansion Port
Chapter 22 Expansion Port...
Page 416: Expansion Port Configuration
MSM66591/ML66592 User's Manual Chapter 22 Expansion Port 22. Expansion Port The MSM66591/ML66592 have a 1-channel internal expansion port for the external expansion of general-purpose ports. The expansion port expands port functions by outputting parallel data of the internal registers as synchronous serial data, and by externally converting serial data to parallel data.
Page 417: Expansion Port Control Register (Extpcon)
MSM66591/ML66592 User's Manual Chapter 22 Expansion Port 22.2 Expansion Port Control Register (EXTPCON) The expansion port control register (EXTPCON) is a 3-bit register that controls the function of the expansion port. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), EXTPCON becomes F8H.
Page 418: Expansion Port Register (Extpd)
MSM66591/ML66592 User's Manual Chapter 22 Expansion Port 22.3 Expansion Port Register (EXTPD) The expansion port register (EXTPD) is a 16-bit buffer register that exchanges data with the exterior via the shift register. 8-bit access is also possible for this register, though only for the lower 8 bits as EXTPDL.
Page 419: Output Mode
MSM66591/ML66592 User's Manual Chapter 22 Expansion Port Output Mode In the output mode, it is assumed that a 74HC595 or other shift register is connected externally. Writing data to EXPTD causes the transfer (output) to start and the EXPBUSY flag to change to "1".
Page 420: Chapter 23 Serial Port With Fifo (Sci5)
Chapter 23 Serial Port with FIFO (SCI5)
Page 422: Sci5 Configuration
Chapter 23 Serial Port with FIFO (SCI5) 23. Serial Port with FIFO (SCI5) The MSM66591/ML66592 have an internal Serial I/O (SCI5) Port with dedicated FIFO that is used for serial synchronous communication with the CAN controller. SCI5 transmits and receives data in 8-bit units in synchronization with the clock specified by SCI5 control register 0 (SCI5CON0).
Page 423: Sci5 Control Register 0 (Sci5Con0)
MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23.2 SCI5 Control Register 0 (SCI5CON0) The SCI5 control register 0 (SCI5CON0) is a 7-bit register that controls SCI5 operation. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SCI5CON0 becomes 10H.
Page 424 MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) SCI5CON0 S5TIE S5RIE S5EXIE — S5RES S5CK2 S5CK1 S5CK0 S5CK SCI5 shift clock 2 1 0 0 0 0 1/4 CLK 0 0 1 1/8 CLK 0 1 0 1/16 CLK...
Page 425: Sci5 Control Register 1 (Sci5Con1)
MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23.3 SCI5 Control Register 1 (SCI5CON1) The SCI5 control register 1 (SCI5CON1) is a 6-bit register that controls SCI5 operation. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SCI5CON1 becomes C0H.
Page 426: Sci5 Interrupt Register (Sci5Int)
MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23.4 SCI5 Interrupt Register (SCI5INT) The SCI5 interrupt register (SCI5INT) is a 3-bit register that controls SCI5 interrupts. At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), SCI5INT becomes 1FH.
Page 427: Serial Address Output Register (Sfadr)
MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23.5 Serial Address Output Register (SFADR) The 8-bit serial address output register (SFADR) specifies the leading address on the CAN controller side. The leading address is accessed when data is transmitted to and received from the CAN controller.
Page 428: Serial Data Input Register (Sfdin)
MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23.6 Serial Data Input Register (SFDIN) The serial data input register (SFDIN) is an 8-bit register used to read the data (stored in the FIFO) received from the CAN controller. This register is read-only. Do not attempt to write to this register.
Page 429: Sci5 Operation
MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23.8 SCI5 Operation During a data transfer, the clock selected by bits 0–2 of SCI5CON0 (S5CK0–S5CK2) becomes the shift clock for SCI5 (SCI5 clock) and is output from the SCLK pin.
Page 430 MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23-9...
Page 431 MSM66591/ML66592 User's Manual Chapter 23 Serial Port with FIFO (SCI5) 23-10...
Page 432: Chapter 24 Ram Monitor Function
Chapter 24 RAM Monitor Function...
Page 434: Configuration Of Ram Monitor Function
In the MSM66Q591/ML66Q592 flash EEPROM version, the RAM monitor function is enabled when the EA pin is set to a "H" level; in the MSM66591/ML66592 mask ROM version, the RAM monitor function is enabled when the TEST pin is set to a "H" level. In the initial state (MSM66Q591/ML66Q592: state where EA pin is at a "L"...
Page 435 MSM66591/ML66592 User's Manual Chapter 24 RAM Monitor Function TEST (for MSM66591/ ML66592) RAM Address Pointer Program Counter (for MSM66Q591/ ML66Q592) Comparator Comparator Control RAM Address Buffer ROM Address Buffer P11_3/RMACK Circuit P11_0/RMRX DOUT P11_1/RMTX 21-bit Shift Register P11_2/RMCLK RAM Data Register...
Page 436: Configuration Of Serial Transfer Data
The desired RAM address to be read can be set within the range from 0000H to 19FFH for the MSM66591 and from 0000H to 21FFH for the ML66592. Data can be read from the set RAM address only if a write operation has been performed. If a read operation is attempted after an instruction other than a write instruction, such as in the case of a counter (including ACC, PSW, etc.) whose contents are changed automatically, incor-...
Page 437 MSM66591/ML66592 User's Manual Chapter 24 RAM Monitor Function 24-4...
Page 438: Ram Monitor Function Operation
ML66Q592, and set the TEST pin to a "H" level for the MSM66591/ML66592. Do not apply a high voltage (more than 5 V) to the EA and TEST pins of the MSM66591/ ML66592 mask ROM version, because those pins of the mask ROM version will be damaged if a high voltage is applied to.
Page 439 In the MSM66Q591/ML66Q592, when the EA pin is brought back to a "L" or "H" level, the RAM monitor function is disabled and the control circuit is initialized. In the MSM66591/ML66592, when the TEST pin is brought back to a "L" level, the RAM monitor function is disabled and the control circuit is initialized.
Page 440 MSM66591/ML66592 User's Manual Chapter 24 RAM Monitor Function 24-7...
Page 441 MSM66591/ML66592 User's Manual Chapter 24 RAM Monitor Function 24-8...
Page 442: Chapter 25 Electrical Characteristics
Chapter 25 Electrical Characteristics...
Page 444: [Msm66591 Electrical Characteristics]
–50 to +150 If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. Applied to TEST, EA. Only for MSM66Q591 Apply a high voltage to the TEST or EA pin after a voltage within the range (4.75 to 5.25 V) guaranteed for operation is applied to V Remove a high voltage from the TEST or EA pin while a voltage within the range (4.75...
Page 445: Operating Range
(the master clock is the frequency generated by multiplying the original oscillation clock by 2). If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. Only for MSM66Q591 25-2...
Page 446: Dc Characteristics
MSM66591/ML66592 User's Manual Chapter 25 Electrical Characteristics 25.3 DC Characteristics MSM66591 = 5 V ±10%, Ta = –40 to +115°C) Parameter Symbol Condition Min. Typ. Max. Unit "H" level input voltage — + 0.3 — "H" level input voltage 0.80V —...
Page 447 85°C, be sure to contact your local Oki sales office in advance. *3 Applied to TEST, EA. Only for MSM66Q591 *4 When programming data into Flash ROM using Oki’s Flash ROM programmer or YDC’s Flash ROM programmer, use a resistor of 1 kΩ or less if connecting an external resistor in series with the TEST pin.
Page 448: Ac Characteristics
The master clock pulse is the frequency generated by multiplying the original oscillation clock by 2. If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. Master clock (CLK) (internal) t ø...
Page 449: A/D Converter Characteristics
(the master clock is the frequency generated by multiplying the original oscillation clock by 2). If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. µF Reference...
Page 450 0.1 µF in the left figure. AI23 or AGND Figure 25-2 Crosstalk Measurement Circuit (MSM66591) Definition of Terminology Resolution Resolution is the value of minimum discernible analog input. – AGND) ÷ 1024 is possible. With 10 bits, since 2...
Page 451: [Ml66592 Electrical Characteristics]
–50 to +150 If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. Applied to TEST, EA. Only for ML66Q592 Apply a high voltage to the TEST or EA pin after a voltage within the range (4.75 to 5.25 V) guaranteed for operation is applied to V Remove a high voltage from the TEST or EA pin while a voltage within the range (4.75...
Page 452: Operating Range
(the master clock is the frequency generated by multiplying the original oscillation clock by 2). If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. Only for ML66Q592 25-9...
Page 453: Dc Characteristics
MSM66591/ML66592 User's Manual Chapter 25 Electrical Characteristics 25.8 DC Characteristics ML66592 = 5 V ±10%, Ta = –40 to +95°C) Parameter Symbol Condition Min. Typ. Max. Unit "H" level input voltage — + 0.3 — "H" level input voltage 0.80V —...
Page 454 85°C, be sure to contact your local Oki sales office in advance. *3 Applied to TEST, EA. Only for ML66Q592 *4 When programming data into Flash ROM using Oki’s Flash ROM programmer or YDC’s Flash ROM programmer, use a resistor of 1 kΩ or less if connecting an external resistor in series with the TEST pin.
Page 455: Ac Characteristics (Preliminary)
2. If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. In the ML66Q592, the electrical characteristics for external memory access apply when the (internal) master clock frequency is 24 MHz or less.
Page 456: A/D Converter Characteristics
(the master clock is the frequency generated by multiplying the original oscillation clock by 2). If this device is used in circumstances where the ambient temperature (Ta) exceeds 85°C, be sure to contact your local Oki sales office in advance. µF Reference...
Page 457 MSM66591/ML66592 User's Manual Chapter 25 Electrical Characteristics ML66592 Crosstalk is defined as the difference between the A/D 5 kW – conversion result when applying the identical analog input to AI0–AI23 and the A/D Analog input conversion result in the circuit 0.1 µF...
Page 458: Chapter 26 Package Dimensions
Chapter 26 Package Dimensions...
Page 460 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
Page 461 MSM66591/ML66592 User's Manual Chapter 26 Package Dimensions 26-2...
Page 462: Chapter 27 Revision History
Chapter 27 Revision History...
Page 464: Feul66591
MSM66591/ML66592 User's Manual Chapter 27 Revision History 27. Revision History Page Document Date Description Previous Current Edition Edition — — Mar. 4, 2002 First edition FEUL66591-66592-01 27-1...
Page 465 MSM66591/ML66592 User's Manual Chapter 27 Revision History 27-2...
Page 466 Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration...

This manual is also suitable for:

Ml66592

Oki MSM66591 User Manual

Chapter 1 Overview

Chapter 2 Description of Pins

Chapter 3 CPU Architecture

Chapter 4 CPU Control Functions

Chapter 5 Memory Control Functions

Chapter 6 Port Functions

Chapter 7 Output Pin Control Pin (OE)

Chapter 8 Clock Generation Circuit

Chapter 9 Time Base Counter (TBC)

Chapter 10 Watchdog Timer (WDT)

Chapter 11 Flexible Timer (FTM)

Chapter 12 General-Purpose 8-Bit Timer Function

Chapter 13 PWM Functions

Chapter 14 Baud Rate Generator Functions

Chapter 15 Serial Port Functions

Chapter 16 A/D Converter Functions

Chapter 17 Transition Detector Functions

Chapter 18 Peripheral Functions

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