Sharp JX-8200 Service Manual page 172

SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
III. R3741 to R3710/40 CONNECTIONS
SysCil*
SysReset*
IOWr*
IORd*
IDT79R3710/40 IOCSx* IDT79R3741
A3
A2
INTx*
pld nSELECTIN
pld nINIT
pld nSTROBE
pld nAUTOFD
BUSY
SELECT
nACK
PERROR
nFAULT
IOData[7..0]
29FCT52
A
CWSTROBE
CLKAB
CRSROBE
CLKBA
OEAB*
CROE*
OEBA*
REG CENx*
CLK
CWOE*
Recommended Centronics Connections
e. Sirial I/F controller
I. Specifications
Fastest data rate of any Am8530
•
8.192 MHz / 2.048 Mb/s
•
10 MHz / 2.5 Mb/s
•
16.384 MHz / 4.096 Mb/s
Low-power CMOS technology
Pin and function compatible with other NMOS and CMOS
8530s
Easily interfaced with most CPUs
•
Compatible with non-multiplexed bus
Many enhancements over NMOS Am8530H
•
Allows Am85C30 to be used more effectively in high-speed
applications
•
Improves interface capabilities
Two independent full-duplex serial channels
Asynchronous mode features
•
Programmable stop bits, clock factor, character length and
parity
•
Break detection/generation
•
Error detection for framing, overrun, and parity
Synchronous mode features
•
Supports IBM® BISYNC, SDLC, SDLC Loop, HDLC, and
ADCCP Protocols
•
Programmable CRC generators and checkers
•
SDLC/HDLC support includes frame control, zero insertion and
deletion, abort, and residue handling
nSELECTIN
nINIT
nSTROBE
nAUTOFD
pld BUSY
pld SELECT
pld nACK
pld PERROR
pld nFAULT
Centronics
74LS245
Data[7..0]
B A B
AB/BA*
OE*
Enhanced SCC functions support high-speed frame reception
using DMA
•
14-bit byte counter
•
10 x 19 SDLC/HDLC Frame Status FIFO
•
Independent Control in both channels
•
Enhanced operation does not allow special receive conditions to
lock the 3-byte DATA FIFO when the 10 x 19 FIFO is enabled
Local Loopback and Auto Echo modes
Internal or external character synchronization
2-Mb/s FM encoding transmit and receive capability using in-
ternal DPLL for 16.384-MHz product
Internal synchronization between R x C to PCLK and T X C to
PCLK
•
This allows the user to eliminate external synchronization
hardware required by the NMOS device when transmitting or
receiving data at the maximum rate of 1/4 PCLK frequency
II. BLOCK DIAGRAM
Internal
Control
Logic
Data 8
CPU
Bus I/O
Control 5
Internal
Interrupt
Control
Control Lines
Logic
+5V GND CLK
III. Signal list (Pin configurations)
D1
D3
D5
D7
INT
IEO
IEI
INTACK
+5V
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
DTR/REQA
RTSA
CTSA
DCDA
PCLK
13 – 13
Baud
Rate
Transmitter
Generator
Receiver
10x19 Bit
Channel
Frame
A
Status
Registers
FIFO
Control
Logic
Channel A
Channel
B
Registers
Channel A
DIP
1 40 D0
2 39 D2
3 38 D4
4 37 D6
5 36 RD
6 35 WR
7 34 A/B
8 33 CE
9 32 D/C
10 31 GND
Am85C30
11 30 W/REQB
12 29 SYNCB
13 28 RTxCB
14 27 RxDB
15 26 TRxCB
16 25 TxDB
17 24 DTR/REQB
18 23 RTSB
19 22 CTSB
20 21 DCDB
T xD A
RxDA
RTxCA
T RxCA
DTR/RE QA
SYNCA
W/REQA
R TS A
C TS A
DCDA
T xD B
RxDB
RTxCB
T RxCB
DTR/RE QB
SYNCB
W/REQB
R TS B
C TS B
DCDB