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SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
PIN NAME
I/O
ALE
I/O
Address Latch Enable: Used to indicate that the A/D bus contains valid address information for the bus transaction.
This signal is used by external logic to capture the address for the transfer, typically using latches.
During cache coherency operations, the R3081 monitors ALE at the start of a DMA write, to assure the write target
address for potential data cache invalidates.
Rd
O
Read: An output which indicates that the current bus transaction is a read.
Wr
I/O
Write: An output which indicates that the current bus transaction is a Write. During coherent DMA, this input indicates
that the current transfer is a Write.
DataEn
O
External Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor during read
cycles, and thus the external memory system may enable the drivers of the memory system onto this bus without having
a bus conflict occur. During write cycles, or when no bus transaction is occurring, this signal is negated, thus disabling
the external memory drivers.
Burst/
O
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that current bus read is requesting a block
WrNear
of four contiguous words from memory. This signal is asserted only in read cycles due to cache misses; it is asserted for
all I-Cache miss read cycles, and for D-Cache miss read cycles if quad word refill is currently selected.
On Write transactions, the WrNear output tells the external memory system that the bus interface unit is performing
back-to-back write transactions to an address within the same 512 word page as the prior write transaction. This signal
is useful in memory systems which employ page mode or static column DRAMs, and allows near writes to be retired
quickly.
Ack
I
Acknowledge: Indicates to the device that the memory system has sufficiently processed the bus transaction, and that
the CPU may either terminate the write cycle process the read data from this read transfer.
During Coherent DMA, this signal indicates that the current write transfer is completed, and that the internal invalidation
address counter should be incremented.
RdCEn
I
Read Buffer Clock Enable: Indicates to the device that the memory system has placed valid data on the A/D bus, and
that the processor may move the data into the on-chip Read Buffer.
SysCIk
O
System Reference Clock: This clock is used to control state transitions in the read buffer, write buffer, memory
controller, and bus interface unit. This clock will either be at the same frequency as the CPU execution rate clock, or at
one-half that frequency, as selected during reset.
BusReq
I
DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface signals so that
they may be driven may be driven by an external master.
BusGnt
O
DMA Arbiter Bus Grant: An output from the CPU used to acknowledge that a BusReq has been detected, and that the
bus is relinquished to the external master.
IvdReq
I
Invalidate Request: An input from an external DMA controller to request that the CPU invalidate the Data Cache line
corresponding to the current DMA write target address.
CohReq
I
Coherent DMA Request: An input used by the external DMA controller to indicate that the requested DMA operations
could involve hardware cache coherency.
SBrCond (3:2)
I
Branch Condition Port: These external signals are internally connected to the CPU signals CpCond (3:0). These
BrCond (0)
signals can be used by the branch on co-processor condition instructions as input ports. There are two types of Branch
Condition inputs: the SBrCond inputs have special internal logic to synchronize the inputs and thus may be driven by
asynchronous agents. The direct Branch Condition inputs must be driven synchronously.
BusError
I
Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error. This signal is only
sampled during read and write operations. If the bus transaction is a read operation, then the CPU will remove bus error.
Int (5:3)
I
Processor Interrupt: During normal operation, these signals are logically the same as the Int (5:0) Slnt (2:0) signals of
the R3000. During processor reset, these signals perform mode initialization of the CPU, but in a different (simpler)
method than the interrupt signals of the R3000.
There are two types of interrupt inputs: the Slnt inputs are internally synchronized by the processor, and may be driven
by an asynchronous external agent. The direct interrupt inputs are not internally synchronized, and thus must be
externally synchronized to the CPU. The direct interrupt inputs have one cycle lower latency than the synchronized
interrupts.
ClKln
I
Master Clock Input: This input clock is used at the CPU (1x clock mode) frequency, or at twice that frequency (2x clock
mode) so that it is selected at reset.
Reset
I
Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last cycle of Reset.
Rsvd (4:1)
I/O
Reserved: These four signal pins are reserved for testing and future revisions of this device.
DESCRIPTION
13 – 5
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