Toshiba T1200 User Manual page 122

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AT00-AT07 are assigned to the odd byte. 2-byte read operation

of display refresh is executed to the V-RAM. When the CPU or

the DMAC reads the V-RAM, two bytes of the RAM is enabled, but

only one of those two bytes is output to the I/O bus BD00-BD07.

This is controlled by UA00 input signal.

When UA00 is at low level, one byte of the CC00-CC07 is output

to the bus BD00-BD07, and when UA00 is at high level, one byte

of the AT00-AT07 is output to the I/O bus BD00-BD07.

When the CPU or the DMAC writes to the V-RAM, two bytes of the

RAM is enabled, but only one of those two

write operation.

WRC0: Write Character Code (Output)

WRA0: Write Attribute Data (Output)

These are the write enable signals to the V-RAM. When the chip

enable signal is low and this signal is also low, write

operation to the RAM is executed.

Write operation to the RAM is executed only when the request

signal from the CPU or the DMAC is generated (when both MSL0

and MEW0 are low). In this case, either WRC0 or WRA0 becomes

low depending on the status of UA00. When UA00 is low, WRC0

becomes also low, and write data appears on the CC00-CC07

through the I/O buses BD00-BD07.

When UA00 is high, WRA becomes low, and the write data appears

on the AT00-AT07 through BD00-BD07.

Page D-13

Address Assignment of the V-RAM

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V-RAM Pin³V-RAM Signal³CPU Address³Memory Refresh³Memory Refresh ³

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