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UA00-UA05, UA14 (A001-A051,A141) : CPU Address (Input)
These are address data line from the CPU or DMAC, and when it
is at high level, it shows logic true.
UA00-UA03 (A0-A3) are used for selecting one of the I/O ports
included in the gate array during read or write operation to
the I/O port of the gate array. When memory read or write
operation to the V-RAM is performed, memory location is
selected by the address lines UA00-UA05 (A0-A5) and also by
those of A06-A13 which are supplied directly to the V-RAM
without passing the gate array.
BD00-BD07 (SD01-SD71): 8-bit Data Bus (
These are 8-bit data lines and when those signals are at high
level, it shows logic true. These lines are used for input or
output of the data during read or write operation to the I/O
port inside the gate array or to the V-RAM.
IORDY1: I/O Ready (Output)
When access requirement to the V-RAM is generated from the
CPU or DMAC, if DMESL0 becomes low, the gate array keeps
this signal at low level, and puts the CPU and DMAC in the
waiting position until the access is enabled.
RST0 (RESET0): (Reset)
When this signal is at low, the gate array is reset.
D.5.2 V-RAM signals (34 lines)
UR00-UR04: CPU/Refresh Address 00-04 (Input)
RA05-RA12: Refresh Address 05-12 (Input)
These are address lines for the V-RAM.
The 5 address signals UR00-UR04 are directly connected to the
address input pin of the V-RAM, while the upper 8 signals on
the address lines RA05-RA12 are multiplexed with the address
signals A061-A131 of the I/O bus and are connected to the
address input pin of the V-RAM.
There are two modes in the accessing the V-RAM; one is the mode
in which memory read or write operation from the CPU is
executed through the I/O bus, and the other is the one in which
the direct display fresh (read only) is performed from the gate
array.
Page D-12
CELO, CEHO : Chip Enable Low/High (Output)
These are the chip enable signals for the V-RAM, and at low
level the RAM is enabled. Only CELO is used in the system. 2
SRAMs (TC5565), configuration of which is 8k x 8, are used as
the RAM.
The RAM connected to the data buses CC00-CC07 are assigned to
the even byte, and the one connected to the data buses
Input/Output)
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