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Page C-1
C.2 FUNCTIONS
This gate array contains the following functions.
- Latches the CPU address and data
- Switches the CPU address/data and those of the DMA.
- Controls the data transfer between the CPU and the I/O bus or the
system bus.
- Decodes the I/O address
- Controls the refresh request
- Contains the back-up register for resuming.
This gate array is composed of 100 pins altogether, and details of
each pin are also included in this section.
MODEL:T1200H/HB
Page C-2
C.3 BUS DRIVER BLOCK DIAGRAM
FIGURE C-1 Block Diagram
Page C-3
- Control Signals -
Meanings of each signal described on the previous page are
as follows.
- CPUDE
The direction of ODD data bus towards the CPU
BDHENùBWDIR
- CPLDE
The direction of EVEN data bus towards the CPU
WDLEN+BDLENùBWDIR
- ALE
Address Latch Enable
- HLDA
Holds Acknowledge signal. During the DMA cycle,
this signal is active.
- IODEN
I/O data bus enable signal.
When a device on the I/O data bus is accessed,
this signal becomes active.
HLDAù(INTA+IODMS)ùHLDAùA9ù
A8ù(OCO-OD)ù(OE5-OEF)
ù(IORD+IOWR)
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