Serr Signal Condition; 4Gb Pcie Hole Granularity; Memory Branch Mode; Branch 0/1 Rank Interleaving - Silicon Graphics Altix XE320 User Manual

6: BIOS Settings
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SERR Signal Condition

4GB PCIe Hole Granularity

Memory Branch Mode

Branch 0/1 Rank Interleaving

Branch 0/1 Rank Sparing

Enhanced x8 Detection

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Caution: Use caution when changing the Advanced settings. Incorrect values entered may cause
a system to malfunction. Also, a very high DRAM frequency or incorrect DRAM timing may
cause system to become unstable. When this occurs, revert the item to the default setting.
This setting specifies the ECC Error conditions. The options are None, Single Bit, Multiple Bit,
and Both.
This feature enables you to specify the size of PCIe hole. The options are: 256 MB, 512 MB, 1GB
and 2GB.
This option determines how the two memory branches operate. System address space can either
be interleaved between the two branches or Sequential from one branch to another. Mirror mode
allows data correction by maintaining two copies of data in two branches. Single Channel 0 allows
a single DIMM population during system manufacturing. The options are Interleave, Sequential,
Mirroring, and Single Channel 0.
Select Enabled to enable the feature of memory Interleaving for Branch 0 Rank/ Branch1 Rank.
The options are 1:1, 1:2 and 1:4.
Select Enabled to enable the sparing feature for Branch 0 Rank/Branch 1 Rank. The options are
Enabled and Disabled.
Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options are Disabled and
Enabled.
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