Intel PXA255 Datasheet page 11

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)
Pin Name Type
L_DD[15]/
ICOCZ
GPIO[73]
MBGNT/
ICOCZ
GP[13]
MBREQ/
ICOCZ
GP[14]
PCMCIA/CF Control Pins
nPOE/
ICOCZ
GPIO[48]
nPWE/
ICOCZ
GPIO[49]
nPIOW/
ICOCZ
GPIO[51]
nPIOR/
ICOCZ
GPIO[50]
nPCE[2]/
ICOCZ
GPIO[53]
nPCE[1]/
ICOCZ
GPIO[52]
nIOIS16/
ICOCZ
GPIO[57]
nPWAIT/
ICOCZ
GPIO[56]
PSKTSEL/
ICOCZ
GPIO[54]
nPREG/
ICOCZ
GPIO[55]
LCD Controller Pins
L_DD(7:0)/
ICOCZ
GPIO[65:58]
L_DD[8]/
ICOCZ
GPIO[66]
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Signal Descriptions
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
Memory controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory controller alternate bus master request.
(input) Allows an external device to request the system
bus from the memory controller.
PCMCIA output enable. (output) Reads from PCMCIA
memory and to PCMCIA attribute space.
PCMCIA write enable. (output) Performs writes to
PCMCIA memory and to PCMCIA attribute space. Also
used as the write enable signal for variable latency I/O.
PCMCIA I/O write. (output) Performs write transactions
to PCMCIA I/O space.
PCMCIA I/O read. (output) Performs read transactions
from PCMCIA I/O space.
PCMCIA card enable 2. (output) Selects a PCMCIA
card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
MMC clock. (output) Clock signal for the MMC controller.
PCMCIA card enable 1. (outputs) Selects a PCMCIA
card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
IO Select 16. (input) Acknowledge from the PCMCIA
card that the current address is a valid 16 bit wide I/O
address.
PCMCIA wait. (input) Driven low by the PCMCIA card to
extend the length of the transfers to/from the PXA255
processor processor.
PCMCIA socket select. (output) Used by external
steering logic to route control, address, and data signals
to one of the two PCMCIA sockets. When PSKTSEL is
low, socket zero is selected. When PSKTSEL is high,
socket one is selected. Has the same timing as the
address bus.
PCMCIA register select. (output) Indicates that the
target address on a memory transaction is attribute
space. Has the same timing as the address bus.
LCD display data. (outputs) Transfers pixel information
from the LCD Controller to the external LCD panel.
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
Memory controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
Package Information
Reset State Sleep State
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [5]
Note[1]
Pulled High -
Note [3]
Note[1]
Pulled High -
Note [3]
Note[1]
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