Table of Contents
Advertisement
Table 2-6
NMG2090 Pin Descriptions (continued)
Pin Name
VAFC Interface (continued)
VCLK
DCLK
BLANK#
VSYNC
HSYNC
Miscellaneous Pins
MTEST#
BUSSEL
CLKRUN#
DDC2BD
DDC2BC
Power Pins
VSSP
GND
DVSS
VSSP
AVSSM
AVSSV
AVSSR1
AVSSR2
Type
Pin No.
I
168
O
147
O
146
O
90
O
89
I
87
I
88
I/O
145
I/O
11
I/O
12
10, 29, 44, 59, 80,
114, 125, 138
123, 64, 109
136, 154, 173
|153
105
104
99
100
Video Clock Pixel' clock driven from the video system to
NM2090chip. It's used as a reference to the data and other
line
Dot lock This is the reference clock driven by NM2090to the
video system
BLANK# This active low output indicates that NM2090is
currently in the blanked region
Vertical SYNC NM2090will drive the vertical sync signal to
the video system on this pin. The polarity of the vertical
sync will depend on the VGA mode selected.
Horizontal SYNC NM2090will drive the horizontal sync
signal to the video system on this pin. The polarity of the
horizontal sync will depend on the VGA mode selected.
Memory Test This active low signal is used for internal
memory testing. This should be tied high for normal system
operation.
Bus Select This pin is used to define the host bus interface
type.
1 = VESA-VL bus
0 = PCI bus
Clockrun The master device will control this signal to the
NMG2, according to the Mobile computing PCI design guide.
If this signal is sampled high by the NM2090and the PCI
clock related functions are not completed then it will drive
this signal low to request the Central Clock Resource for the
continuation of the PCI clock. This function can be
Enabled/Disabled through reg GR12 bit 4.
DDC Data pin
DDC Clock pin
Host bus interface ground
Logic ground
DRAM ground
VAFC interface ground
Analog ground for MCLK synthesizer
Analog ground for MCLK synthesizer
Analog ground for VCLK synthesizer
Analog ground for DAC current reference
Descriptions
Advertisement
Table of Contents
