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Passive power management cuts power consumption when the system is idle
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Supports SMM (system management mode), SMI (system management interrupt), Stop
Clock, and AutoHalt
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Flexible hybrid voltage implementation
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Optional thermal control with thermal clock throttling
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User-programmable power setting (10 percent granularity)
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Deep Sleep and Suspend-to-Disk modes
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Supports wake control, interrupt-as-wake-source, and ring-output-as-wake-source
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External activity detection
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Status indicator
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Supports 3.3-V processor bus, 3.3V/5-V PCI bus, 5-V ISA bus, 3.3V L2 cache controller,
and 3.3V/5-V DRAM subsystem
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Supports both toggle and linear burst sequences
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Supports CPU address pipelining and burst read/write
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Supports eight-level write-buffer for DRAM and PCI cycles
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Integrated 64-bit write-through and write-back Level 2 (L2) cache controller
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Direct-mapped
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Supports cache size of 256 Kbytes to 1 Mbyte with 32byte line size
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Supports synchronous or asynchronous 3.3-V SRAM
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Internal and external TAG compare
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Supports 2-1-1-1 burst read and write with 10 ns synchronous (15 ns cycle time) SRAM
and with 8 ns TAG RAM at 66-MHz and O1-1-1 with 10 ns synchronous SRAM and
internal TAG compare at 66-MHz
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One less wait-state for read lead-off cycle with pipelining
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Supports S2-2-2 burst write with 17 ns asynchronous SRAM and 15 ns TAG SRAM with
internal TAG compare at 66-MHz
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Intelligent L2 cache power management, including stop dock for synchronous SRAMs,
and TAG chip select for TAGRAM
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Supports 64-bit 2-way set associative writeback cache with Sony's Sonyc-2WP
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Built-in DRAM controller
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Mixable 64- or 32-bit DRAM bank support
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3.3-V and 5-V DRAM support
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Up to 256 Mbytes of system memory
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Four banks of 64-bit DRAM or eight banks of 32-bit DRAM
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Supports 256 Kbit, 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbits, and 16 Mbit DRAM
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Support for symmetric and asymmetric DRAM
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