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Pin Descriptions
This section contains a detailed functional description of the pins on V1-LS.
reference, the pins are arranged alphabetically within each of the following functional interface
groups:
•
CPU Interface (CPU)
•
DRAM Interface (DRAM)
•
L2 Cache Interface (L2 CACHE)
•
PCI Interface (PCI)
•
Power Management Interface (PMC)
•
V1 -GS / V2-LS Interface (V1-LS / V2-LS)
•
V1 -GS / V3-LS Interface (V1 -GS / V3-LS)
•
Reset and Clock Interface (RESET / CLOCK)
•
Power and Ground (POWER / GROUND)
The '#' symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage. Signal names without the '#' symbol indicate that the signal is active,
or asserted at the high voltage level.
The '/' symbol between signal names indicates that the signals are multiplexed or have dual
functionality and use the same pin for all functions.
The following conventions have been used to describe the pin type: 'I' = input-only pins; 'O' =
output-only pins; and 'I/O' = bi-directional pins. The pin type is defined relative to the Vesuvius
platform.
For a list of pins arranged by pin name, refer to the following table.
Table 2-2
V1-LS Pin Descriptions
Pin Name
Pin No.
CPU Interface
A20M#
58
A[28:3]
205:198,
19:9,
5:1,
208:206
Type
O
ADDRESS BIT 20 MASK#: This output to the CPU indicates that
the CPU should mask A20 in order to emulate the 8086 address
wrap around.
I/O
CPU ADDRESS LINES [28:3]: These are address lines that
together with the byte enable signals (BE[7:0]) make the address
bus and define the physical area of memory or l/O accessed and
are driven as outputs during DMA and bus master cycles.
NOTE: CPU's unused pins [31:29] should be pulled down by 1K-
4.7K resistors for proper snooping.
Description
For ease of
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