Table of Contents
Advertisement
Table 2-2
V1-LS Pin Descriptions (continued)
Pin Name
Pin No.
V1-LS / V2-LS Interface (continued)
BDCTL[2:0]
189:191
DECBUF
194
INCBUF
192
PCIMSTR#
179
V2CLK
22
V1-LS / V3-LS Interface
BSER1TO3
141
BSER3TO1
140
Reset and Clock Interface
32KHZCK
147
CLKIN
138
BSERCLKV3
141
PWRGOOD
142
RCRST#
146
RSTDRV
143
SPNDNRST
145
Type
0
BDCTL[2:0]: Data path control signals to V2-LS.
O
DECREMENT WRITE BUFFER COUNTER: This output is used to
decrease the pointer on the eight-level write buffer.
O
INCREMENT WRITE BUFFER COUNTER: This output is used to
increase the pointer on the eight-level write buffer.
O
PCI MASTER#: Indicates to V2-LS that V1-LS is responding to a
PCI master cycle.
O
V2 CLOCK: Clock for the interface between V1-LS and V2-LS.
O
SERIAL BUS: Serial bus interface from V1-LS to V3-LS.
I
SERIAL BUS: Serial bus interface from V3-LS to V1-LS.
I
CLOCK: Clock source used for DRAM controller and power
management functions.
I
CLOCK: Input clock source to CPU clock. CMOS level 50/5- duty
cycle is recommended.
O
CLOCK: Clock for the serial interface between V1-LS and V3-LS.
I
POWER GOOD INPUT: This input causes a complete system
reset. It is driven by the PWRGOOD signal from the power supply
or a reset switch. On power up, PWRGOOD going from low to
high indicates that external VCC is stable and will wake up V1-LS
from Standby to On. If PWRGOOD goes low, it will drive the chip
back to Standby.
I
RC RESET#: This input is used to reset V1-LS' power
management controller upon initial system power-up. It should
have a pull-up resistor tied to the same power source as V1-LS.
O
AT BUS RESET OUTPUT: This output provides a system reset
O
SUSPEND NOT RESET: This output provides a reset equivalent to
RSTDRV except when in Suspend Mode. During Resume
SPNDNRST will not pulse so that any device not powered down
during Suspend Mode should use this reset. NOTE: Do not
connect thin pin for V1-LS; this pin is only applicable to V1
Description
Advertisement
Table of Contents
