Table of Contents
Advertisement
Table 2-10
NS87336VLJ Pin Descriptions (continued)
Pin
No.
IORCHDY
53
IRQ3, 4
1, 100
IRQ5-7
98-96,
IRQ9-11
57-59,
IRQ12, 15
68, 60
IRRX1
67, 68
IRRX2
IRTX
65
MR
2
I/O
Description
O
I/O Channel Ready.
extends the host cycle.
I/O
Interrupt 3, 4, 5, 6, 7, 9, 10, 11, 12, and 15. This pin can be a
totem-pole output or an open-drain output.
sourced by one of the following: UART1 and/or UART2, parallel port,
FDC, SIRQI1 pin, SIRQI2 pin or SIRQI3 pin.
IRQ5 is multiplexed with ADRATE0.
IRQ12 is multiplexed with /DSR2 and IRRX2.
IRQ15 is multiplexed with SIRQ11.
I
IrDA or SHARP- Infrared Receive. One of these pins is the infrared
serial data input.
IRRX1 is multiplexed with SIN2.
IRRX2 is multiplexed with /DSR2 and IRQ12.
O
Infrared
Transmit.
configuration selects either IrDA or Sharp-IR protocol.
This pin is multiplexed with SOUT2/BOUT/CFG0.
I
Master Reset. Active high output that resets the controller to the idle
state and resets all disk interface outputs to their inactive states. The
DOR, DSR, CCR, Mode command, Configure command, and Lock
command parameters are cleared to their default values.
Specify command parameters are not affected
When IORCHDY is driven low, the EPP
Infrared
serial
data
The interrupt can be
output.
Software
The
Advertisement
Table of Contents
