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Table E-1
POST Checkpoint List
Checkpoint
• Enables UIE, then checks RTC update cycle
68h
• Parallel port testing
70h
• Serial port testing
74h
• Math coprocessor testing
78h
• Reset pointing device
7Ch
• Set security status
80h
• KB device initialization
84h
• Set KB led upon setup requests
• Enable KB device
• Issue 2nd software SMI to communicate with PMU
86h
• Enable the use of BIOS Setup, system information. and fuel gauge
• Tests and initializes FDD
6Ch
• HDD testing & parameter table setup
88h
• Initializes HDD enhanced features
• Displays POST status if necessary
90h
• Changes POST mode to default text mode
• Initializes I/O ROM
94h
• Shadows I/O ROM if setup requests
• Builds up free expansion ROM table
• Initializes PCI Card ROM
96h
• Writes ESCD data into NVRAM
• Writes ESCD data into NVRAM
97h
• Initializes timer counter for DOS use
A0h
• Initializes security feature
A4h
• Enables NMI
ACh
• Enables parity checking
• Sets video mode
• Issues 3rd software SMI to communicate with PMU
AEh
• Starts all power management timers
• Checks whether system is resumed from 0V suspend or not.
Note: The RTC executes an update cycle per second. When the UIE is set, an
interrupt (IRQ8) occurs after every update cycle and indicates that over
999ms are available to read valid time and date information.
Note: The FDD LED should flash once and its head should be positioned.
Note: I/O ROM is an optional extension of the BIOS located on an installed add-on
card as a part of the I/O subsystem. POST detects I/O ROMs and gives
them opportunity to initialize themselves and their hardware environment.
Description
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