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Table 2-4
V3-LS Pin Descriptions (continued)
Pin Name
ISA Interface (continued)
SD[15:0]
SMEMR#
SMEMW#
SPKR
SYSCLK
TC
ZWS#
PCI Interface
AD[31:0]
C/BE[3:0]#
DEVSEL#
Pin No.
Type
157, 158,
I/O
SLOT DATA[15:0]: These l/Os are the data read and write path
160:164,
for the AT bus.
166:172,
174, 175
8
O
SLOT MEMORY READ#: This output to the AT bus indicates
that a Memory Read cycle is within the lower 1 Mbyte address
range.
7
O
SLOT MEMORY WRITE#: This output to the AT bus indicates
that a Memory Write cycle is within the lower 1 Mbyte address
range.
83
O
SPEAKER: Speaker data output.
64
O
SYSTEM CLOCK: AT bus clock. It is derived from BSERCLKV3
and the divisor is selectable by register ATCR-1 bit [2:0].
4
O
TERMINAL COUNT: Signal on the ISA bus indicating that a
terminal count has reached for a given channel.
176
I
ZERO WAIT STATE#: This input from the AT bus indicates that
the device currently being accessed can complete the cycle with
zero wait states
92,
I/O
ADDRESS/DATA MULTIPLEXED [31:0]: These signals are
94:97,
multiplexed on the same pins. Each transaction is initiated by a
100:102,
32-bit physical address phase which is followed by one or more
105,
data phases. These bus transactions support both read and
107:110,
write bursts.
112, 114,
115, 127,
129:131,
133:136,
138, 140,
141,
143:147
103, 116,
I/O
COMMAND/BYTE ENABLES [3:0]#: Both are multiplexed on
126, 137
the same pins. The pins define the Bus Command during the
address phase. During the data phase, the pins are used as
Byte Enables.
120
I/O
DEVICE SELECT#: As an output it indicates whether Vesuvius
is the target of the current address. As an input, Vesuvius sees
whether or not a PCI target exists.
Description
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