Acer AcerNote 970 Service Manual page 60

The V1-LS supports power management features like SMM, SMI, Stop Clock, and AutoHalt. It also
features a thermal control mechanism that uses CPU clock throttling to efficiently control the
power consumption and heat dissipation associated with the processor.
The V2-LS data path controller provides a 64-bit data path between the CPU and the main
memory; a 32-bit data path between the CPU bus and the PCI local bus, and a 32-bit data path
between the PCI local bus and the main memory. The eight-level deep, 64-bit write-buffers
implemented in the V2-LS device are quad-word-wide and substantially improve the CPU-to-
memory and the CPU-to-PCI write performance. The VESUVIUS architecture offers a cost-
efficient interface between the V2-LS and V1-LS devices, enabling a single chip implementation of
the entire data path control.
The V3-LS chip completes the VESUVIUS solution for desktop/portable systems. Its primary
function is to act as a bridge between the PCI and the ISA bus. The V3-Gs provides interface
between the PCI local bus and the industry-standard ISA expansion bus. It has the logic to support
master and slave cycles on both PCI and ISA buses. The V3-LS integrates most l/O functions such
as DMA controllers, interrupt controllers, programmable interval timer, memory mapper, and
hidden ISA refresh controller found in ISA-based personal computers.
The V3-LS isolates the PCI bus and the ISA bus by providing the data buffers and buffer control
logic. It has a special serial interface with V1-LS to support power management features including
ISA bus device activity detection and other PicoPower-proprietary features. Additionally, the V3-
LS supports proven ISA hot/warm docking by appropriately tri-stating the ISA bus. Available in a
176-pin TQFP package, the V3-LS chip also contains a highly integrated peripheral controller.
Features
•
Optimized three-chip PCI system controller solution for Intel's Pentium™ processors
•
Universal support for AMD's K5 and Cyrix's M1 64-bit processors
•
Supports all 3.0v processors with speeds up to 100 MHz
•
Supports processor bus frequencies of 50-, 60-, and 66-MHz
•
Native PCI Local Bus architecture with direct connection to the Pentium processor bus
•
Vesuvius-LS: Ideally suited for entry-level to midrange portable systems and energy-efficient
desktop computers
•
Supports L1 (level-1) write-back or write-through cache protocols
•
Space-efficient, two 208-pin and one 176-pin TQFP packages
•
0.6-µm CMOS technology
•
100% IBM-AT compatible
•
PicoPower's exclusive Power on Demand lIl
•
Best-of-class power and thermal management
•
Employs PicoPower's patented Power on Demand technologies to achieve superior
power efficiency
•
Active power management cuts power consumption even when the system is in use