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Table 2-11
ESS1688W Pin Descriptions (continued)
Pin name
Number
Digital Pins
A0-A9
96-100, 1, 2,
5-7
A10-A11
94,95
AEN
8
D0-D7
10-17
ENB245
18
DS0, DS1
26, 27
IS0, IS1
22, 23
AMODE
21
I/O
I
Address inputs from ISA bus.
I
Address inputs from ISA bus. The ES1688W requires these
pins to be low for all address decodes. These pins have an
internal pulldown device enabled when input signal AMODE=0.
In this case they can float (ES688 compatible designs).
I
Active low address enable from ISA bus.
I/O
Bi-directional data bus. These pins have weak pull-up devices
to prevent these inputs from floating when not driven.
O
Active low output when ES1688W is being read or written to.
Intended to be connected to the enable control of an external
74LS245.
I
Inputs with internal pull-down devices. These inputs select the
DMA channel selected after external reset:
DS1
DS0
0
0
0
1
1
0
1
1
DSl=0 and DS0=0 is a special case: no DMA request or
interrupt request pin is selected after external reset. Software
configuration of interrupt and DMA channels are required.
I
Inputs with internal pull-down devices. These inputs select the
default interrupt request pin selected after external reset (unless
DS1 =0 and DS0=0).
IS1
IS0
0
0
0
1
1
0
1
1
I
Input pin with internal pulldown device. If this pin is low, then
AS0 and ASI act as in the ES688, namely, they directly select
the base address of the ESI680 I/O address bank. If this pin is
high, then AS0 and ASI can be configured to select one of two
software address selection techniques.
Description
DRQx/DACKBx
Recommended ISA DRO/DACK
No DRQ or DACK
DRQA, DACKBA
DRQ0/-DACK0
DRQB, DACKBB
DRQ1/-DACK1
DRQC, DACKBC
DRQ3/-DACK3
IRQX
Recommended ISA IRQ
IRQA
IRQ9
IRQB
IRQ5
IRQC
IRQ7
IRQD
IRQl0
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