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BIOS POST Checkpoints
This appendix lists the POST checkpoints of the notebook BIOS.
Table E-1
POST Checkpoint List
Checkpoint
• Determines if the current booting procedure is from cold boot (press reset button
04h
• Disables Non-Maskable Interrupt (NMI), Alarm Interrupt Enable (AIE), Periodical
08h
• Initializes Vesuvius ChipSet V1-LS, V2-LS and V3-LS
09h
• DMA(8237) testing & initialization
10h
• System timer (8254) testing & initialization
14h
• Memory refresh test; refresh occurrence verification (IRQ0)
18h
• Verifies CMOS shutdown byte, battery and check sum
1Ch
• The CMOS shutdown byte verification assures that CMOS 0Fh area is fine to
• Initializes CMOS default setting
• Initializes RTC time base
• DRAM type determination (FPM or EDO type)
1Dh
• DRAM sizing, 32/64 bit Memory Accessing
1Eh
• Tests 128K base memory
2Ch
or turn the system on), from warm boot (press
setup.
Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to
determine whether this POST is caused by a cold or warm boot. If it is a
cold boot, a complete POST is performed. If it is a warm boot, the chip
initialization and memory test is eliminated from the POST routine.
Interrupt Enable (PIE), and Update-ended Interrupt Enable (UIE).
Note: These interrupts are disabled in order to avoid any mis-action happened
during the POST routine.
Note: Several parts of the POST routine require the system to be in protected
mode. When returning to real mode from protected mode, the processor is
reset, therefore POST is re-entered. In order to prevent re-initialization of
the system, POST reads the shutdown code stored in location 0Fh in CMOS
RAM. Then it jumps around the initialization procedure to the appropriate
entry point.
execute POST properly.
Note: The RTC has an embedded oscillator that generates 32.768 KHz frequency.
To initial RTC time base, turn on this oscillator and set a divisor to 32768 so
that RTC can count time correctly.
Note: The 128K base memory area is tested for POST execution. The remaining
memory area is tested later.
A p p e n d
A p
p e n d i x
Description
b
a
^
+
+
), or from exiting BIOS
i x
E
E
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