Table of Contents
Advertisement
Table 2-14
CL-PD6730 Pin Descriptions (continued)
Pin Name
PCI Bus Interface Pins (continued)
PERR#
Parity Error: The CL-PD6730 drives this input
active (low) if it detects a data parity error during a
write phase.
SERR#
System Error: This output is pulsed by the CL-
PD6730 to indicate an address parity error.
PAR
Parity: This pin is sampled the clock cycle after
completion of each corresponding address or write
data phase. For read operations this pin is driven
from the cycle after TRDY# is asserted until the
cycle after completion of each data phase. It
ensures even parity across AD[31:0] and
C/BE[3:0]#.
PCI_CLK
PCI Clock: This input provides timing for all
transactions on the PCI bus to and from the CL-
PD6730. All PCI bus interface signals described in
this table, except RST#, INTA#, INTB#, INTC#,
and INTD#, are sampled and driven on the rising
edge of PCI_CLK; and all CL-PD6730 PCI bus
interface timing parameters are defined with
respect to this edge. This input can be operated at
frequencies from 0 to 33 MHz.
Note that the PC Card socket interface cannot
operate at more than 25 MHz.
RST#
Device Reset: This input is used to initialize all
registers and internal logic to their reset states and
place most CL-PD6730 pins in a high-impedance
state.
INTA#/
PCI Bus Interrupt A / ISA Interrupt Request 9:
IRQ9
This output indicates a programmable interrupt
request generated from any of a number of card
actions. Although there is no specific mapping
requirement for connecting interrupt lines from the
CL-PD6730 to the system, a common use is to
connect this pin to the PCI bus INTA# interrupt
line and using PCI Interrupt Signaling mode. In
External-Hardware Interrupt Signaling mode, this
pin indicates interrupt request IRQ9.
Description
Pin Number
I/O
33
O-TS
34
O-TS
35
I/O
1
207
203
O-TS
Power
4
4
4
4
Advertisement
Table of Contents
