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Table 2-6
NMG2090 Pin Descriptions (continued)
Pin Name
VL Interface (continued)
BLAST#
RESET#
LCLK
RDYRTN#
LDEV#
LRDY#
BRDY#
INTR#
/A24
VID2#
/A26
IDSEL#,
/A27
Clock Interface
XTAL1
XTAL2
Type
Pin No.
I
66
I
84
I
71
I
73
O
69
S/T/S
O
68
S/T/S
O
67
S/T/S
O-o/d
70
I
I
79
I
81
I
93
O
92
Burst Last This input indicates the completion of a burst
cycle.
Reset This active low signal initializes the NM2090to a
known state.
Local Clock This is a 1X clock with the same phase as 486
type CPU.
Ready Return This input establishes a handshake between
the VESA-VL bus master and NMG2. It is used by the local
bus controller to generate LRDY#.
Local Device This active Low output indicates that the
NM2090will respond to the current cycle.
Local Ready This active low output is used to terminate the
claimed cycle.
Burst Ready This active low output terminates the current
active burst cycle.
Interrupt Request / Address 24 This active low output
indicates as interrupt to CPU/ Address bit 24.( GR12 bit 0
enables/disables the Address 24 decoding ).
Low Address Decode/Address 26 This input signal is used
as upper address decode during memory cycles. It is
decoded from A31-A24 to select low meg address space.
For a value of zero for the addresses A31-A24 VID2 should
go low. /Address bit 26 ( GR12 bit 2 enables/disables the
Address 26 decoding ).
High Address Decode This input signal is used as upper
address decode during memory cycles active low signal is
the decode to support accesses to the linear memory and
memory mapped IO ports/Address bit 27(GR12 bit 2
enables/disables the Address 27 decoding).
Crystal lnput This is the X1 pin of the on-chip oscillator for
crystal use. This pin can also be used to feed the 14.31818
MHz from an external clock source.
Crystal Output This pin is used for the 14.31818 MHz clock
internally to NM2090chip when a crystal oscillator is
connected between this pin and pin 93.
Descriptions
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