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Table 2-15
PCI0643 Signal Descriptions (continued)
Signal
DSD[15:0]
36-39,
50-53,
62-65,
71-74
ENIDE
21
FRAME#
98
IDSEL#
100
INTA#
84
IRDY#
99
IRQ14
22
IRQ15
83
PAR
96
Pin
Type
B/T
Disk Data bits 0 through 15. These are 16-bit bidirectional
data bus that connects to the IDE drive(s). DSD[7:0] define
the lowest data byte while the DSD [15:8] define the most
significant data byte. The DSD bus is normally in a high-
impedance state and is driven by the PCI0643 only during the
DIOW# command pulse.
I
Enable IDE. This is an active high input that enables the
PCI0643's default mode disk operation following reset. When
set to low, the PCI0643 is disabled following reset. This mode
allows software to scan for system hardware and enable the
PCI0643 via the PCME register (index 4). When left floating or
pulled high, the PCI0643 is enabled and cannot be disabled
via software.
S/T/S
Cycle Frame. This is driven by the current master to indicate
the beginning and the duration of an access.
asserted to indicate that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue. When FRAME#
is de-asserted, the transaction is in the final data phase.
I
Initialization Device Select. This pin is used as a chip select
during configuration read and write transactions.
O/D
Interrupt A. This is used to request an interrupt in PCI IDE
Native Mode. INTA# is tristated when both IDE port are in
Legacy Mode.
S/T/S
Initiator Ready.
master's) ability to complete the current data phase of the
transaction. This signal is used with TRDY#. A data phase is
completed on any clock when both IRDY# and TRDY# are
sampled asserted. Wait cycles are inserted until both IRDY#
and TRDY# are asserted together.
T/O
IRQ14. This is used to request an interrupt in PCI IDE legacy
Mode (for PC-AT compatibles). IRQ14 is tristated when IDE
port 0 is in Native Mode.
T/O
IRQ15. This is used to request an interrupt in PCI IDE legacy
Mode (for PC-AT compatibles). IRQ15 is tristated when IDE
port 1 is in Native Mode.
B/T
Parity. PAR is even parity across AD[31:0] and C/BE[3:0]#.
Parity generation is required by all PCI agent. PAR is stable
and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted on a write transaction or
TRDY# is asserted on a read transaction. Once PAR is valid,
it remains valid until one clock after the completion of the
current data phase. (PAR has the same timing as ad[31:0] but
delayed by one clock).
Description
This indicates the initializing agent's (bus
FRAME# is
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