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The '#' symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage. Signal names without the # symbol indicate that the signal is active,
or asserted at the high voltage level.
The '/' symbol between signal names indicates that the signals are multiplexed and use the same
pin for all functions.
The following conventions have been used to describe the pin type: 'I' = input-only pins; 'O' =
output-only pins; and 'I/O' = bi-directional pins. The pin type is defined relative to the Vesuvius
platform.
For a list of pins arranged by pin name, refer to the following table.
Table 2-3
V2-LS Pin Descriptions
Pin Name
Pin No.
CPU Interface
D[63:0]
67:40,
38:22,
20:8, 6,
4:1,
208:205
DRAM Interface
MD[63:0]
204:195,
193:186,
184,
182:178,
176,
174:159,
157,
155:142,
140,
138:131
PCI Interface
AD[31:0]
91:94,
97:100,
1012:105,
107,
109:115,
117:120,
122:125,
127:130
FRAME#
108
Type
I/O
CPU DATA BUS D[63:0]: These are the upper and lower bits of
the 64-bit Pentium processor data bus.
I/O
DRAM DATA BUS: These pins are dedicated DRAM array data
pins. These pins are inputs during DRAM read cycles and
outputs during DRAM write cycles.
I/O
ADDRESS/DATA MULTIPLEXED [31:0]: These signals are
multiplexed on the same pins. Each transaction is initiated by a
32-bit physical address phase which is followed by one or more
data phases. These bus transactions support both read and
write bursts. AD[31:0] are also used as IDSELs in the
Configuration Cycle.
I
FRAME#: FRAME# is driven by the current initiator and
indicates the start and duration of the transaction. FRAME# is
deasserted to indicate that the initiator is ready to complete the
final data phase. A transaction may consist of one or more data
transfers between the current initiator and the currently-
addresses target.
Description
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