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Table 2-15
PCI0643 Signal Descriptions (continued)
Signal
PCICLK
89
PCIGNT#
82
PCIMODE
2
PCIREQ#
81
PERR#
95
RESET#
1
STOP#
97
TEST0
85
TRDY#
92
VDD
16, 41, 67,
91
VSS
15, 27, 40,
54, 66, 90
Pin
Type
I
Clock Signal. This signal provides timing for all transaction
on PCI and is an input to every PCI device. All other PCI
signals, except RESET# and IRQ, are sampled on the rising
edge of PCICLK, and all other timings with respect to this
edge.
I
PCI Grant. This signal indicates to the agent that access to
the PCI bus has been granted.
I
PCI Mode. This is et to high when chip is used in PCI bus.
T/O
PCI Request. This signal indicates to the arbiter that this
agent desires use of the PCI bus.
S/T/S
Pulsed Error. Error may be pulsed active by an agent that
detects a parity error. PERR# can be used by any agent to
signal data corruption. However, on detection of a PERR#
pulse, the central resource may generate a non-Maskable
interrupt to the host CPU which often implies that the system
is unable to continue operation once an error processing is
completed.
I
Reset. This is an active high input that is used to set the
internal registers of the PCI0643 to their initial state. RESET#
is typically the system power-on reset signal as distributed on
the PCI bus.
S/T/S
Stop. This indicates that the current target is requesting the
master to stop the current transaction.
I
TEST0. This pin is used with DIOCS16# when PCIMODE-0 to
select different DC tests for this chip.
S/T/S
Target Ready. This indicates that the target agent's ability to
complete the current data phase of the transaction. TRDY# is
used with IRDY#. A data phase is completed on any clock
when both TRDY# and IRDY# are sampled asserted. During a
read, TRDY# indicates that valid data is present on AD(31:0).
During a write, it indicates the target is prepared to accept
data.
I
3V Positive Power Supply Input.
I
Ground Reference Input.
Description
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